MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1751

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 27 Inter IC (I2C)
or reading of data or starting a new command, all control and data writes to the registers
are stored in the write FIFO. Multiple commands (control and supporting data) can be
written back-to-back as long as the write FIFO is not full. The read FIFO is used only during
2
2
an I
C read. This data will also be queued up by the I
C logic.
This FIFO data is read back through the HW_I2C_QUEUEDATA register. If there are
multiple read data words in the queue, the next one will be immediately available after a
read from the data register. So, it is possible for software to wait until multiple words are
available and then do multiple or burst reads from the HW_I2C_QUEUEDATA register.
The HW_I2C_QUEUECTRL_QUEUE_RUN bit may be set after the commands are queued
up or before. If the bit is set while the write FIFO is empty, then the logic will wait until
the control word is written. Care must be taken that control words and data are written in
the proper order as explained above; otherwise, commands will not execute properly.
The read and write FIFOs are managed with a watermark or FIFO threshold mechanism
and an interrupt per FIFO. The HW_I2C_QUEUECTRL_WR_THRESH and
HW_I2C_QUEUECTRL_RD_THRESH fields set the threshold values. These values are
in units of words which is the basic unit of the FIFOs. For
HW_I2C_QUEUECTRL_WR_THRESH, the associated interrupt bit will assert whenever
the number of words in the FIFO is less than or equal to the threshold value. For
HW_I2C_QUEUECTRL_RD_THRESH, the associated interrupt bit will assert whenever
the number of words in the FIFO is greater than or equal to the threshold value. Note that
the associated interrupt bits will assert whether or not the interrupt is enabled back to the
2
processor. These threshold and interrupts will allow the CPU to be notified when the I
C
channel needs to be serviced and eliminates the need for software to poll for transaction
status.
27.4 Behavior During Reset
A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set
CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See
Correct Way to Soft Reset a Block
for additional information on using the SFTRST and
CLKGATE bit fields.
27.4.1 Pinmux Selection During Reset
2
For proper I
C operation, the appropriate pinmux(s) must be selected before taking the
2
block out of reset. Failure to select the I
C pinmux selections before taking the block out
2
2
of reset will cause the I
C clock to operate incorrectly and will require another I
C hardware
reset.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.
1751