MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1261

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

16.2 Operation
Before performing any NAND flash read or write operations, software should first program
the BCH's flash layout registers (see
formatted on the flash device. The BCH hardware allows full programmability over the
flash page layout to enable users flexibility in balancing ECC correction levels and
ever-changing flash page sizes.
To initiate a NAND Flash write, software will program a GPMI DMA operation. The DMA
need only program the GPMI control registers (and handle the requisite flash addressing
handshakes) since the BCH will handle all data operations using its AXI bus interface. The
BCH will then send the data to the GPMI controller to be written to flash as it computes
the parity symbols. At the end of each data block the BCH will insert the parity symbols
into the data stream so that the GPMI sees only a continuous stream of data to be written.
NAND Flash read operations operate in a similar manner. As the GPMI controller reads
the device, all data is sent to the BCH hardware for error detection/correction. The BCH
controller writes all incoming read data to system memory and in parallel computes the
syndromes used to detect bit errors. If errors are detected within a block, the BCH hardware
Freescale Semiconductor, Inc.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
GPMI clock domain
CONTROLLER
Programmable
Figure 16-1. Hardware BCH Accelerator
Registers
NAND
GPMI
GPMI
APBH
Read Data
Write Data
Flash Page
Programmable
Registers
Calculation
Syndrome
BCH
Equation
Solver
Search
Transfer Controls
Chien
Key
error-locator polynomial
syndromes
synpar
APBH Bridge/DMA
AXI
Generation
Parity
Layout) to specify how data is to be
BCH Engine
Chapter 16 20-BIT Correcting ECC Accelerator (BCH)
Read Data
corrections
Write Data
transfer
master
FSM
AXI
&
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