MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1144

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
14.8.37 DRAM Control Register 39 (HW_DRAM_CTL39)
This is a DRAM configuration register.
Address:
Re-
14.8.38 DRAM Control Register 40 (HW_DRAM_CTL40)
This is a DRAM configuration register.
1144
set
Bit
W
R
OBSOLETE
31
RSVD1
0
RSVD1
RSVD1
31 30
29 24
23 16
TCPD
TCKE
TFAW
TDLL
Field
23 8
Field
15 0
7 3
2 0
30
0
29
0
HW_DRAM_CTL39
28
0
Not all memories use this parameter. If tDAL is defined in the memory specification, then program this
parameter to the specified value. If the memory does not specify a tDAL time, then program this parameter
to tWR + tRP. DO NOT program this parameter with a value of 0x0 or the EMI will not function properly
when auto pre-charge is enabled.
DRAM TCPD parameter in cycles.
Defines the clock enable to pre-charge delay time for the DRAM devices, in cycles.
Always write zeroes to this field.
Minimum CKE pulse width.
Defines the minimum CKE pulse width, in cycles.
Always write zeroes to this field.
DRAM TFAW parameter in cycles.
Defines the DRAM tFAW parameter, in cycles.
Always write zeroes to this field.
DRAM TDLL parameter in cycles.
Defines the DRAM DLL lock time, in cycles.
TFAW
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_DRAM_CTL38 field descriptions (continued)
24
0
23
0
HW_DRAM_CTL39 field descriptions
800E_0000h base + 9Ch offset = 800E_009Ch
22
0
21
0
OBSOLETE
20
0
19
0
18
0
17
0
16
0
15
0
Description
Description
14
0
13
0
12
0
11
0
10
0
0
9
TDLL
0
8
Freescale Semiconductor, Inc.
0
7
0
6
0
5
0
4
3
0
0
2
0
1
0
0