MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 818

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
the interrupt collector as interrupt GPIO0. For example, if this register contains 0x00000014,
then only bits 2 and 4 in HW_PINCTRL_IRQSTAT0 (corresponding to pins GPIO0[2] and
GPIO0[4]) will cause interrupts from bank 0.
Address:
Re-
9.4.64 PINCTRL Bank 1 Interrupt Mask Register (HW_PINCTRL_IRQEN1)
The PINCTRL Bank 1 Interrupt Mask Register contains interrupt enable masks for the pins
in bank 1.
HW_PINCTRL_IRQEN1: 0x1110
HW_PINCTRL_IRQEN1_SET: 0x1114
HW_PINCTRL_IRQEN1_CLR: 0x1118
HW_PINCTRL_IRQEN1_TOG: 0x111C
As described earlier in this chapter, any digital I/O pin can be used as an interrupt source.
This register masks the interrupt sources from the pins in bank 1. If a bit is set in this register
and the same bit is set in HW_PINCTRL_IRQSTAT1, an interrupt will be propagated to
the interrupt collector as interrupt GPIO1. For example, if this register contains 0x00000014,
then only bits 2 and 4 in HW_PINCTRL_IRQSTAT1 (corresponding to pins GPIO1[2] and
GPIO1[4]) will cause interrupts from bank 1.
818
set
Bit
W
R
31
RSRVD1
RSRVD1
0
IRQEN
31 29
Field
28 0
30
0
29
0
HW_PINCTRL_IRQEN0
28
0
Empty Description.
Each bit in this register corresponds to one of the 29 pins in bank 0:
1= Enable interrupts from the corresponding bit in HW_PINCTRL_IRQSTAT0.
0= Disable interrupts from the corresponding bit in HW_PINCTRL_IRQSTAT0.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
HW_PINCTRL_IRQEN0 field descriptions
23
0
22
0
8001_8000h base + 1100h offset = 8001_9100h
21
0
20
0
19
0
18
0
17
0
16
0
15
0
Description
IRQEN
14
0
13
0
12
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
0
6
0
5
0
4
3
0
0
2
0
1
0
0