MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 423

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

6.5.53 APBH DMA Channel 6 Buffer Address Register
The APBH DMA Channel 6 buffer address register contains a pointer to the data buffer for
the transfer. For immediate forms, the data is taken from this register. This is a byte address
which means transfers can start on any byte boundary.
This register holds a pointer to the data buffer in system memory. After the command values
have been read into the DMA controller and the device controlled by this channel, then the
DMA transfer will begin, to or from the buffer pointed to by this register.
Address:
Re-
6.5.54 APBH DMA Channel 6 Semaphore Register
The APBH DMA Channel 6 semaphore register is used to synchronize between the CPU
instruction stream and the DMA chain processing state.
Freescale Semiconductor, Inc.
set
Bit
W
R
ADDRESS
31
0
Field
31 0
30
0
Field
29
0
(HW_APBH_CH6_BAR)
(HW_APBH_CH6_SEMA)
HW_APBH_CH6_BAR
28
0
Address of system memory buffer to be read or written over the AHB bus.
27
0
26
0
HW_APBH_CH6_CMD field descriptions (continued)
10- read transfer
11- SENSE
0x0
0x1
0x2
0x3
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
NO_DMA_XFER — Perform any requested PIO word transfers but terminate command before
any DMA transfer.
DMA_WRITE — Perform any requested PIO word transfers and then perform a DMA transfer
from the peripheral for the specified number of bytes.
DMA_READ — Perform any requested PIO word transfers and then perform a DMA transfer
to the peripheral for the specified number of bytes.
DMA_SENSE — Perform any requested PIO word transfers and then perform a conditional
branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense
is false. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is true.
0
HW_APBH_CH6_BAR field descriptions
23
0
22
0
8000_4000h base + 3D0h offset = 8000_43D0h
21
0
20
0
19
0
18
0
17
0
Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
ADDRESS
16
0
15
0
Description
Description
14
0
13
0
12
0
11
0
10
0
0
9
0
8
0
7
0
6
0
5
0
4
3
0
0
2
0
1
423
0
0