MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1766

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
27.5.8 I2C Queue Status Register. (HW_I2C_QUEUESTAT)
This register exposes the state of the internal read and write queues used in PIO Queue
mode.
HW_I2C_QUEUESTAT: 0x070
HW_I2C_QUEUESTAT_SET: 0x074
HW_I2C_QUEUESTAT_CLR: 0x078
HW_I2C_QUEUESTAT_TOG: 0x07C
This information can be useful during debug or by the CPU during normal operation.
Address:
1766
Reset
Reset
WR_QUEUE_
Bit
Bit
W
W
IRQ_EN
R
R
Field
RSVD2
[15:15]
0
31
15
0
0
HW_I2C_QUEUESTAT
30
14
0
0
Set this bit to one to enable receiving interrupts from the WR_QUEUE_IRQ source to the interrupt collector.
Set to zero to disable interrupts from the I2C controller.
0x0
0x1
29
13
0
1
HW_I2C_QUEUECTRL field descriptions (continued)
DISABLED — Interrupt source disabled.
ENABLED — Interrupt source enabled.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
0
0
RD_QUEUE_CNT
27
11
0
0
8005_8000h base + 70h offset = 8005_8070h
26
10
0
0
25
0
0
9
RSVD2[31:16]
24
0
0
8
Description
23
0
0
7
22
0
0
6
21
0
5
1
20
0
4
0
Freescale Semiconductor, Inc.
WR_QUEUE_CNT
19
0
0
3
18
0
0
2
17
0
0
1
16
0
0
0