MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 400

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
6.5.32 APBH DMA Channel 3 Buffer Address Register
The APBH DMA Channel 3 buffer address register contains a pointer to the data buffer for
the transfer. For immediate forms, the data is taken from this register. This is a byte address
which means transfers can start on any byte boundary.
This register holds a pointer to the data buffer in system memory. After the command values
have been read into the DMA controller and the device controlled by this channel, then the
DMA transfer will begin, to or from the buffer pointed to by this register.
Address:
Re-
6.5.33 APBH DMA Channel 3 Semaphore Register
The APBH DMA Channel 3 semaphore register is used to synchronize between the CPU
instruction stream and the DMA chain processing state.
Each DMA channel has an 8 bit counting semaphore that is used to synchronize between
the program stream and and the DMA chain processing. DMA processing continues until
the DMA attempts to decrement a semaphore that has already reached a value of zero. When
the attempt is made, the DMA channel is stalled until software increments the semaphore
count.
Address:
Re-
400
set
set
Bit
Bit
W
W
R
R
ADDRESS
31
31
0
0
Field
31 0
30
30
0
0
29
29
0
0
(HW_APBH_CH3_BAR)
(HW_APBH_CH3_SEMA)
HW_APBH_CH3_BAR
HW_APBH_CH3_SEMA
RSVD2
28
28
0
0
Address of system memory buffer to be read or written over the AHB bus.
27
27
0
0
26
26
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
0
24
24
0
0
HW_APBH_CH3_BAR field descriptions
23
23
0
0
22
22
0
0
8000_4000h base + 280h offset = 8000_4280h
8000_4000h base + 290h offset = 8000_4290h
21
21
0
0
PHORE
20
20
0
0
19
19
0
0
18
18
0
0
17
17
0
0
ADDRESS
16
16
0
0
15
15
0
0
Description
14
14
0
0
13
13
0
0
RSVD1
12
12
0
0
11
11
0
0
10
10
0
0
0
0
9
9
0
0
8
8
Freescale Semiconductor, Inc.
0
0
7
7
INCREMENT_SEMA
0
0
6
6
0
0
5
5
0
0
4
4
3
0
3
0
0
0
2
2
0
0
1
1
0
0
0
0