MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 169

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

HW_ICOLL_INTERRUPT9_CLR: 0x1B8
HW_ICOLL_INTERRUPT9_TOG: 0x1BC
This register provides a mechanism to specify the priority associated with an interrupt bit.
In addition, this register controls the enable and software generated interrupt. WARNING:
Modifying the priority of an enabled interrupt may result in undefined behavior. You should
always disable an interrupt prior to changing its priority.
EXAMPLE
HW_ICOLL_INTERRUPT9_SET(0,0x00000001);
Address:
Freescale Semiconductor, Inc.
Reset
Reset
PRIORITY
Bit
Bit
SOFTIRQ
W
W
RSRVD1
ENABLE
R
R
ENFIQ
Field
31 5
1 0
4
3
2
31
15
0
0
HW_ICOLL_INTERRUPT9 8000_0000h base + 1B0h offset = 8000_01B0h
30
14
0
0
Always write zeroes to this bitfield.
Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through
the main IRQ FSM and priority logic.
0x0
0x1
Set this bit to one to force a software interrupt.
0x0
0x1
Enable the interrupt bit through the collector.
0x0
0x1
Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest).
0x0
0x1
29
13
0
0
DISABLE — Disable
ENABLE — Enable
NO_INTERRUPT — turn off the software interrupt request.
FORCE_INTERRUPT — force a software interrupt
DISABLE — Disable
ENABLE — Enable
LEVEL0 — level 0, lowest or weakest priority
LEVEL1 — level 1
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_ICOLL_INTERRUPT9 field descriptions
28
12
0
0
27
11
0
0
RSRVD1[15:5]
26
10
0
0
25
0
0
9
RSRVD1[31:16]
24
0
0
8
Description
23
0
0
7
22
0
0
6
21
0
5
0
Chapter 5 Interrupt Collector (ICOLL)
20
0
4
0
19
0
0
3
18
0
0
2
PRIORITY
17
0
0
1
16
0
0
0
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