MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1039

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

13.3.14 DCP Work Packet 5 Status Register (HW_DCP_PACKET5)
This register displays the values for the current work packet offset 0x14 (Buffer Size) field.
This register shows the contents of the bytecount register from the packet being processed.
The field can be considered either a byte count or a buffer size. The logic treats this as a
decrmenting count of bytes from the buffer size programmed into the field. As the transaction
proceeds, the logic will decrement the bytecount as data is written to the destination buffer.
For blit operations, the top 16-bits of this field represents the number of lines (y size) in the
blit and the lower 16-bits represent the number of bytes in a line (x size).
Address:
Re-
13.3.15 DCP Work Packet 6 Status Register (HW_DCP_PACKET6)
This register displays the values for the current work packet offset 0x1C (Payload Pointer)
field.
This register shows the contents of the payload pointer fieldr from the packet being processed.
Address:
Re-
Freescale Semiconductor, Inc.
set
set
Bit
Bit
W
W
R
R
31
31
0
0
COUNT
ADDR
Field
31 0
Field
31 0
30
30
0
0
29
29
0
0
HW_DCP_PACKET5
HW_DCP_PACKET6
28
28
0
0
Byte Count register. This value is the working value and will update as the operation proceeds.
This regiser reflects the payload pointer for the current control packet.
27
27
0
0
26
26
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
0
24
24
0
0
23
23
0
0
HW_DCP_PACKET5 field descriptions
HW_DCP_PACKET6 field descriptions
8002_8000h base + D0h offset = 8002_80D0h
8002_8000h base + E0h offset = 8002_80E0h
22
22
0
0
21
21
0
0
20
20
0
0
19
19
0
0
18
18
0
0
17
17
0
0
COUNT
ADDR
16
16
0
0
15
15
0
0
Description
Description
14
14
0
0
13
13
0
0
12
12
0
0
11
11
0
0
10
10
0
0
Chapter 13 Data Co-Processor (DCP)
0
0
9
9
0
0
8
8
0
0
7
7
0
0
6
6
0
0
5
5
0
0
4
4
3
0
3
0
0
0
2
2
0
0
1
1
1039
0
0
0
0