MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1817

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

29.4.6.3 Ipv4 and Ipv6 Priority Look Up
29.4.6.3.1 Overview
The switch can classify both Ipv4 and Ipv6 frames: A 64-Entry Table is implemented per
port to classify the IPv4 Frames and a 256-Entry Table is implemented per port to classify
IPv6 Frames (The IP COS Tables) (see registers IP_PRIORITY).
On the IPv4 COS table entry, the Frame's 6-Bit DiffServ field is provided and the Table
returns the 3-bit priority information.
On the Ipv6 COS table entry, the 8-Bit Class of Service field is provided and the Table
returns the 3-bit priority information.
29.4.6.3.2 Classification Table Programming Model
To program the mapping tables a indirect addressing scheme is implemented using a single
register
Freescale Semiconductor, Inc.
IP_PRIORITY
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
within the register interface.
Figure 29-6. IP COS Tables Overview
Figure 29-5. VLAN Table Overview
8
Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH)
2
Programming Interface
Programming Interface
Ipv6 COS Table
Ipv4 COS Table
256 Entries
IP COS Table
VLAN Table
VLAN Table
8 Entries
64 Entries
3
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