MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1955

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

30.4.9 UART Debug Register (HW_UARTAPP_DEBUG)
The UART Debug Register contains the state of the DMA signals.
Freescale Semiconductor, Inc.
RXCOUNT
RXBYTE_
INVALID
23 20
OERR
BERR
PERR
RXFE
FERR
RXFF
TXFF
Field
15 0
26
25
24
19
18
17
16
Receive FIFO Full.
Transmit FIFO Full.
Receive FIFO Empty.
The invalid state of the last read of Receive Data. Each bit corresponds to one byte of the RX data. (1 =
invalid.)
Overrun Error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by
any write to the Status Register. The FIFO contents remain valid since no further data is written when the
FIFO is full; only the contents of the shift register are overwritten. The CPU must now read the data in order
to empty the FIFO.
Break Error. For PIO mode, this is for the last character read from the data register. For DMA mode, it will
be set to 1 if any received character for a particular RXDMA command had a Break Error. To clear this bit,
write a zero to it. Note that clearing this bit does not affect the interrupt status, which must be cleared by
writing the interrupt register.
Parity Error. For PIO mode, this is for the last character read from the data register. For DMA mode, it will
be set to 1 if any received character for a particular RXDMA command had a Parity Error. To clear this bit,
write a zero to it. Note that clearing this bit does not affect the interrupt status, which must be cleared by
writing the interrupt register.
Framing Error. For PIO mode, this is for the last character read from the data register. For DMA mode, it
will be set to 1 if any received character for a particular RXDMA command had a Framing Error. To clear
this bit, write a zero to it. Note that clearing this bit does not affect the interrupt status, which must be cleared
by writing the interrupt register.
Number of bytes received during a Receive DMA command.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_UARTAPP_STAT field descriptions (continued)
Description
Chapter 30 Application UART (AUART)
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