MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 431

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

This register holds a pointer to the data buffer in system memory. After the command values
have been read into the DMA controller and the device controlled by this channel, then the
DMA transfer will begin, to or from the buffer pointed to by this register.
Address:
Re-
6.5.61 APBH DMA Channel 7 Semaphore Register
The APBH DMA Channel 7 semaphore register is used to synchronize between the CPU
instruction stream and the DMA chain processing state.
Each DMA channel has an 8 bit counting semaphore that is used to synchronize between
the program stream and and the DMA chain processing. DMA processing continues until
the DMA attempts to decrement a semaphore that has already reached a value of zero. When
the attempt is made, the DMA channel is stalled until software increments the semaphore
count.
Address:
Re-
Freescale Semiconductor, Inc.
set
set
Bit
Bit
W
W
R
R
ADDRESS
31
31
0
0
PHORE
RSVD2
RSVD1
31 24
23 16
Field
31 0
Field
15 8
30
30
0
0
29
29
0
0
(HW_APBH_CH7_SEMA)
HW_APBH_CH7_BAR
HW_APBH_CH7_SEMA
RSVD2
28
28
0
0
Address of system memory buffer to be read or written over the AHB bus.
Reserved, always set to zero.
This read-only field shows the current (instantaneous) value of the semaphore counter.
Reserved, always set to zero.
27
27
0
0
26
26
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
0
24
24
0
0
HW_APBH_CH7_SEMA field descriptions
HW_APBH_CH7_BAR field descriptions
23
23
0
0
22
22
0
0
8000_4000h base + 440h offset = 8000_4440h
8000_4000h base + 450h offset = 8000_4450h
21
21
0
0
PHORE
20
20
0
0
19
19
0
0
18
18
0
0
17
17
0
0
Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
ADDRESS
16
16
0
0
15
15
0
0
Description
Description
14
14
0
0
13
13
0
0
RSVD1
12
12
0
0
11
11
0
0
10
10
0
0
0
0
9
9
0
0
8
8
0
0
7
7
INCREMENT_SEMA
0
0
6
6
0
0
5
5
0
0
4
4
3
0
3
0
0
0
2
2
0
0
1
1
431
0
0
0
0