MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1949

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

30.4.5 UART Line Control 2 Register (HW_UARTAPP_LINECTRL2)
HW_UARTAPP_LINECTRL2: 0x040
HW_UARTAPP_LINECTRL2_SET: 0x044
HW_UARTAPP_LINECTRL2_CLR: 0x048
HW_UARTAPP_LINECTRL2_TOG: 0x04C
The UART Line Control 2 Register contains integer and fractional part of the baud rate
divisor value. It also contains the line control bits.
Address:
Freescale Semiconductor, Inc.
Reset
Bit
W
R
STP2
Field
FEN
EPS
PEN
BRK
4
3
2
1
0
31
0
HW_UARTAPP_LINECTRL2
A040h
30
0
Enable FIFOs. If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO mode). When
cleared to 0, the FIFOs are disabled (character mode); that is, the FIFOs become 1-byte-deep holding
registers.
Two Stop Bits Select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive
logic does not check for two stop bits being received.
Even Parity Select. If this bit is set to 1, even parity generation and checking is performed during transmission
and reception, which checks for an even number of 1s in data and parity bits. When cleared to 0, then odd
parity is performed which checks for an odd number of 1s. This bit has no effect when parity is disabled by
Parity Enable (PEN, bit 1) being cleared to 0.
Parity Enable. If this bit is set to 1, parity checking and generation is enabled, else parity is disabled and no
parity bit added to the data frame.
Send Break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing
transmission of the current character. For the proper execution of the break command, the software must
set this bit for at least two complete frames. For normal use, this bit must be cleared to 0.
HW_UARTAPP_LINECTRL field descriptions (continued)
29
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
0
27
0
8006_A000h base + 40h offset = 8006_
26
0
25
0
BAUD_DIVINT
24
0
Description
23
0
22
0
21
0
Chapter 30 Application UART (AUART)
20
0
19
0
18
0
17
0
1949
16
0