MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 424

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
Each DMA channel has an 8 bit counting semaphore that is used to synchronize between
the program stream and and the DMA chain processing. DMA processing continues until
the DMA attempts to decrement a semaphore that has already reached a value of zero. When
the attempt is made, the DMA channel is stalled until software increments the semaphore
count.
Address:
Re-
6.5.55 AHB to APBH DMA Channel 6 Debug Information
This register gives debug visibility into the APBH DMA Channel 6 state machine and
controls.
This register allows debug visibility of the APBH DMA Channel 6.
424
set
Bit
W
R
INCREMENT_
31
0
PHORE
RSVD2
RSVD1
31 24
23 16
SEMA
Field
15 8
7 0
30
0
29
0
(HW_APBH_CH6_DEBUG1)
HW_APBH_CH6_SEMA
RSVD2
28
0
Reserved, always set to zero.
This read-only field shows the current (instantaneous) value of the semaphore counter.
Reserved, always set to zero.
The value written to this field is added to the semaphore count in an atomic way such that simultaneous
software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads
back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA
channel decrements the count on the same clock, then the count is incremented by a net one.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
HW_APBH_CH6_SEMA field descriptions
23
0
22
0
8000_4000h base + 3E0h offset = 8000_43E0h
21
0
PHORE
20
0
19
0
18
0
17
0
16
0
15
0
Description
14
0
13
0
RSVD1
12
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
INCREMENT_SEMA
0
6
0
5
0
4
3
0
0
2
0
1
0
0