MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1151

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MCIMX286CVM4B

Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r

Specifications of MCIMX286CVM4B

Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
14.8.47 DRAM Control Register 51 (HW_DRAM_CTL51)
This is a DRAM configuration register.
Address:
Re-
14.8.48 DRAM Control Register 52 (HW_DRAM_CTL52)
This is a DRAM configuration register.
Freescale Semiconductor, Inc.
set
Bit
W
AXI1_EN_SIZE_
R
AXI1_FIFO_
TYPE_REG
LT_WIDTH_
PRIORITY
PRIORITY
31
AXI1_W_
AXI1_R_
0
RSVD2
RSVD1
INSTR
31 16
15 11
Field
Field
10 8
1 0
7 3
2 0
30
0
29
0
HW_DRAM_CTL51
28
AXI1_EN_SIZE_LT_WIDTH_INSTR
0
Clock domain relativity between AXI port 1 and core logic.
Allow narrow instructions from AXI port 1 requestors with bit enabled.
Always write zeroes to this field.
Priority of write cmds from AXI port 1.
Always write zeroes to this field.
Priority of read cmds from AXI port 1.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_DRAM_CTL50 field descriptions (continued)
24
0
23
0
HW_DRAM_CTL51 field descriptions
800E_0000h base + CCh offset = 800E_00CCh
22
0
21
0
20
0
19
0
18
0
17
0
16
0
15
0
Description
Description
14
0
RSVD2
13
0
12
0
Chapter 14 External Memory Interface (EMI)
11
0
10
PRIORITY
0
AXI1_W_
0
9
0
8
0
7
0
6
RSVD1
0
5
0
4
3
0
PRIORITY
0
2
AXI1_R_
0
1
1151
0
0

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