MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1078

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

EMI AHB and AXI Interface
The logic uses a variety of factors to determine when to issue bank open and close commands.
The logic reviews the entire Command Queue for look-ahead of which banks are to be
accessed in the future. The timing is then set to meet the trc and tras_min timing parameters
of the memory devices, values which were programmed into the memory controller on
initialization. This flexibility allows the memory controller to be tuned to extract the
maximum performance out of memory devices. The parameters that relate to DRAM device
protocol are listed in the “EMI Parameter Descriptions” Chapter.
14.4.13 Latency
By using the placement logic of the command queue in the core logic, a new request through
any port can be immediately placed at the top of the command queue or can interrupt an
ongoing request. This scheme allows a high priority request to be serviced in the shortest
possible time.
However, since there are many factors that determine the placement into the command
queue, there are also many factors that affect the actual latency of the command. These
factors include:
If all of the placement conditions are met, then a new command would be placed at the top
of the command queue. However, if the new command is of a higher priority than the
transaction that is executing, the current command will be interrupted and the new command
will execute first. The interruption will occur at a natural burst boundary of the DRAMs.
The interrupted transaction will be placed at the top of the placement queue and it will
resume after the new request is completed. The page status of the new transaction determines
when the current transaction is interrupted. If the page for the new transaction is already
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• The coherency status of the transactions already in the command queue: If there is a
• The priority status of the transactions already in the command queue: If the new
• The read, write, and bank information of the transactions already in the command queue:
data coherency conflict with a transaction already in the command queue, the new
transaction will be placed after the transaction that produced the conflict. The position
of the conflicting transaction determines the latency of the high priority read or write
command.
command has a higher priority than those already in the command queue, the new
request will be serviced ahead of the lower priority command. As a result, the latency
of the new command will be lower than the latency of the older command.
In general, reads will be placed ahead of writes when both are of the same priority level.
Read commands are grouped with other read commands of similar priorities and write
commands are grouped with other write commands of similar priorities. Among these
groupings, transactions with similar bank and different row destinations are separated
as much as possible.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.