MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2071

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MCIMX286CVM4B

Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r

Specifications of MCIMX286CVM4B

Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
LCD_DATA[15:0]
LCD_WR_RWn
The LCDIF has flexible pin and strobe timings which enable it to optimally support a wide
range of LCDs. The minimum cycle time is two CLK_DIS_LCDIFn cycles (TDS=TDH=1).
For example, this results in a maximum LCD data rate of 12 MB/s when CLK_DIS_LCDIFn
is 24 MHz. TDS and TDH are 8-bit values, so the minimum LCDIF period is 510
Freescale Semiconductor, Inc.
LCD_WR_RWn
LCD_DATA[23:0]
LCD_RD_E
LCD_RD_E
LCD_VSYNC
LCD_RS
LCD_CS
(6800)
LCD_WR
(8080)
(8080)
(6800)
LCD_WR
LCD_CS
LCD_RS
(6800)
(8080)
IDLE
IDLE
Figure 33-11. LCD Interface Signals in MPU Write Mode
Figure 33-12. LCD Interface Signals in MPU Read Mode
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
START
TCS
START
TCS
VSYNC_PULSE_WIDTH
W1+W3
W1+
W3
WR/RD
WR/RD
TDSR
TDSW
LATCH
LATCH
TDHW
TDHR
Data0
Data0
W2
W2
TDSW
WR/RD
WR/RD
TDSR
Chapter 33 LCD Interface (LCDIF)
LATCH
TDHW
Data1
LATCH
Data1
TDHR
STOP
TCH
STOP
TCH
IDLE
IDLE
2071

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