MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1262

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Operation
activates the error correction logic to determine where bit errors have occurred and ultimately
correct them in the data buffer in system memory. After an entire flash page has been read
and corrected, the BCH will signal an interrupt to the CPU.
Figure 16-2
As the BCH receives data from the GPMI (top row), it is written to memory by the BCH's
Bus Interface Unit (BIU) (second row). For blocks requiring correction, the KES logic will
be activated after the entire block has been received. Once the error locator polynomial has
been computed, the corrections are determined by the Chien Search and fed back to the
BIU, which performs a read, modify, write operation on the buffer in memory to correct
the data.
16.2.1 BCH Limitations and Assumptions
1262
• The BCH is programmable to support 2, 4, 6, 8, 10, 12, 14, 16, 18, and 20 bit error
• Data block sizes must be a multiple of 4 bytes and be aligned in system memory.
• The BCH supports a programmable number of metadata/auxiliary data bytes, from 0
• Metadata will be written at the beginning of the flash page to facilitate fast access for
• Metadata may be treated as an independent block for ECC purposes or combined with
• The BCH does not support a partial page write (this can be accomplished by
correction. ECC0 is supported as a passthrough, non-correcting mode.
to 255.
filesystem operations.
the first data block to conserve bits in the flash.
programming the BCH layout registers such that the BCH only sees a portion of the
page).
indicates how data read from the GPMI is operated on within the BCH hardware.
Chien Search
Syndrome
GPMI/
KES
BIU
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Figure 16-2. Block Pipeline while Reading Flash
Block 0
Block 0
Read
Write
Block 0
Block 1
Block 1
KES
Read
Write
Block 2 /
Block 2
Correct
Block 0
Block 1
Block 0
Read
Write
KES
CS
Block 2
Block 1
Block 3 /
KES
Block 3
Correct
Block 1
Read
Write
CS
Block 2
Block 3
Block 4 /
Correct
Block 2
Block 4
KES
CS
Read
Write
Block 3
Block 5 /
Block 4
Block 5
Correct
Block 3
Read
KES
Write
CS
Block 5
Block 6 /
Block 4
Block 6
Correct
Block 4
KES
Read
Write
CS
Block 5
Block 7 /
Block 6
Block 7
Correct
Block 5
KES
Read
Write
CS
Block 7
Block 6
Correct
Block 6
KES
CS
Block 7
Correct
Block 7
CS
Freescale Semiconductor, Inc.
ECC Done
Interrupt