MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1951

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

The UART Interrupt Register contains the interrupt enables and the interrupt status. The
interrupt status bits report the unmasked state of the interrupts. To clear a particular interrupt
status bit, write the bit-clear address with the particular bit set to 1. The enable bits control
the UART interrupt output: a 1 will enable a particular interrupt to assert the UART interrupt
output, while a 0 will disable the particular interrupt from affecting the interrupt output. All
the bits, except for the modem status interrupt bits, are cleared to 0 when reset. The modem
status interrupt bits are undefined after reset.
Address:
Freescale Semiconductor, Inc.
Reset
Reset
DSRMIEN
Bit
Bit
W
W
R
R
ABDIEN
RSVD1
OEIEN
RXIEN
BEIEN
PEIEN
FEIEN
RTIEN
TXIEN
31 28
Field
27
26
25
24
23
22
21
20
19
31
15
0
0
HW_UARTAPP_INTR
30
14
0
0
RSVD1
RSVD2
Reserved, read as zero, do not modify.
Automatic Baudrate Detected Interrupt Enable.
Overrun Error Interrupt Enable.
Break Error Interrupt Enable.
Parity Error Interrupt Enable.
Framing Error Interrupt Enable.
Receive Timeout Interrupt Enable.
Transmit Interrupt Enable.
Receive Interrupt Enable.
nUARTDSR Modem Interrupt Enable. This bit is not supported.
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
0
0
HW_UARTAPP_INTR field descriptions
8006_A000h base + 50h offset = 8006_A050h
27
11
0
0
OEIS
26
10
0
0
BEIS
25
0
0
9
PEIS
24
0
0
8
Description
FEIS
23
0
0
7
RTIS
22
0
0
6
TXIS
21
0
5
0
Chapter 30 Application UART (AUART)
RXIS
20
0
4
0
19
0
0
3
18
0
0
2
17
0
0
1
1951
16
0
0
0