MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 503

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Under a normal operation mode, when termination occurs, DMA would stop the current
descriptor and discard any data remaining in the FIFO. By setting TERMINATEFLUSH
bit in the descriptor command word, DMA will flush out all the remainder data in the FIFO
to system memory for write DMA operation before issue HOT IRQ.
Therefore, it is recommended that software use this signal as follows:
To start processing the first time, software creates the command list to be processed. It
writes the address of the first command into the HW_APBX_CHn_NXTCMDAR register,
and then writes a 1 to the counting semaphore in HW_APBX_CHn_SEMA. The DMA
channel loads HW_APBX_CHn_CURCMDAR register and then enters the normal state
machine processing for the next command. When the software writes a value to the counting
semaphore, it is added to the semaphore count by hardware, protecting the case where both
hardware and software are trying to change the semaphore on the same clock edge.
Software can examine the value of HW_APBX_CHn_CURCMDAR at any time to determine
the location of the command structure that is currently being processed.
7.3 DMA Chain Example
The example in the following figure shows how to bring the basic items together to make
a simple DMA chain to read PCM samples and send them out the Audio Output (DAC)
using one DMA channel. This example shows three command structures linked together
using their normal command list pointers. The first command writes a single PIO word to
the HW_AUDIOOUT_CTRL0 register with a new word count for the DAC. This first
command also performs a 512 byte DMA_READ operation to read the data block bytes
into the DAC. A second and a third DMA command structure also performs a DMA_READ
operation to handle circular buffer style outputs. The completion of each command structure
generates an interrupt request. In addition, each command structure decrements the
Freescale Semiconductor, Inc.
1. Reset the channel.
2. Determine the error from error reporting in the peripheral block, then manage the error
• Always set HALTONTERMINATE to 1 in a DMA descriptor. That way, if a peripheral
• When an IRQ from an APBH/X channel is received, and the IRQ is determined to be
signals HOT, the transfer will end, leaving the peripheral block and the DMA engine
synchronized (but at the end of a command).
due to an error (as opposed to an IRQONCOMPLETE interrupt) the software should:
in the peripheral that is attached to that channel in whatever appropriate way exists for
that device (software recovery, device reset, block reset, and so on).
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA)
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