MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 105

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

1.3.15.1 Bose Ray-Choudhury Hocquenghem ECC Engine
The Bose, Ray-Chaudhuri, Hocquenghem (BCH) Encoder and Decoder module is capable
of correcting from 2 to 20 single bit errors within a block of data not larger than about 900
bytes (512 bytes is typical) in applications such as protecting data and resources stored on
modern NAND Flash devices. The correction level in the BCH block is programmable to
provide flexibility for varying applications and configurations of flash page size. The design
can be programmed to encode protection of 2, 4, 8, 10, 12, 14, 16, 18, or 20 bit errors when
writing into the flash and to correct the corresponding number of errors on decode. The
correction level when decoding MUST be programmed to the same correction level as that
was used during the encode phase.
BCH-codes are a type of block-code, which implies that all error-correction is performed
over a block of N-symbols. The BCH operation will be performed over GF (2
which is the Galois Field consisting of 8191 one-bit symbols. BCH encoding (or encode
for any block-code) can be performed by either of the two algorithms: systematic encoding
or multiplicative encoding. Systematic encoding is the process of reading all the symbols
which constitute a block. These symbols are divided continuously by the generator
polynomial for the GF (8192) and the resulting t parity symbols are appended to the block
to create a BCH codeword (where t is the number of correctable bits).
The BCH sits on the AXI fabric with close coupling to both the GPMI and the external
memory controller.
See
1.3.16 Data Co-Processor (DCP) Memory Copy, Crypto
The device contains a data co-processor consisting of four virtual channels. Each channel
is essentially a memory-to-memory copy engine. The linked list control structure can be
used to move the byte-aligned blocks of data from a source to the destination. In the process
of copying from one place to another, the DCP can be programmed to encrypt or decrypt
the block using AES-128 in one of the several chaining modes. An SHA-1 or SHA256 hash
can be calculated as part of the memory-copy operation.
See
Freescale Semiconductor, Inc.
BCH Overview
Data Co-Processor (DCP) Overview
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
for more information.
for more information.
Chapter 1 Product Overview
13
= 8192),
105