MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2303

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

an LRADC channel, providing continuous acquisitions of the conversions executed, delayed
by the value specified in the DELAY field. The delay channel is started by setting the KICK
bit to one.
EXAMPLE
HW_LRADC_DELAYn_WR(3, (BF_LRADC_DELAYn_TRIGGER_LRADCS(0x05)
each time
kHz clock
//
Address:
Re-
Freescale Semiconductor, Inc.
set
Bit
W
R
LOOP_COUNT
TRIGGER_
TRIGGER_
31
LRADCS
RSRVD2
0
DELAYS
... do other things until the triggered LRADC channels report an interrupt.
DELAY
31 24
23 21
19 16
15 11
KICK
Field
10 0
20
30
TRIGGER_LRADCS
0
29
0
HW_LRADC_DELAY3
28
0
Setting a bit in this bit field to one causes the delay controller to trigger the corresponding LRADC channel.
This trigger occurs when the delay count of this delay channel reaches zero. Note that all eight LRADC
channels can be triggered at the same time. Any channel with its corresponding bit set in this field is triggered.
The HW accomplishes this by setting the corresponding bit(s) in HW_LRADC_CTRL0_SCHEDULE.
Reserved
Setting this bit to one initiates a delay cycle. At the end of that cycle, any TRIGGER_LRADCS or
TRIGGER_DELAYS will start.
Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel.
This trigger occurs when the delay count of this delay channel reaches zero. Note that all four delay channels
can be triggered at the same time, including the one that issues the trigger. This can have the effect of
automatically retriggering a delay channel.
This bit field specifies the number of times this delay counter will count down and then trigger its designated
targets. This is particularly useful for scheduling multiple samples of an LRADC channel set. If this field is
set to 0x0, then exactly one delay loop will be generated with exactly one event triggering the target LRADC
and/or delay channels.
ERRATA: TA1 and TA2 silicon revisions do not correctly support the LOOP_COUNT field, do not use.
This 11-bit field counts down to zero. At zero it triggers either a set of LRADC channel conversions or another
delay channel, or both. It can trigger up to all eight LRADCs and all four delay channels in a single event.
This counter operates on a 2KHz clock derived from crystal clock.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
BF_LRADC_DELAYn_KICK(1)
BF_LRADC_DELAYn_TRIGGER_DELAYS(0x8)
BF_LRADC_DELAYn_DELAY(0x0E45) ) );
24
0
HW_LRADC_DELAY3 field descriptions
23
RSRVD2
0
22
0
8005_0000h base + 100h offset = 8005_0100h
21
0
20
0
19
0
Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface
TRIGGER_
DELAYS
18
0
17
0
16
0
15
0
Description
LOOP_COUNT
14
0
13
0
12
0
11
0
| // LRADC channel 0 and 2
| // Start the Delay channel
| // restart delay channel 3
10
0
// delay 3653 periods of 2
0
9
0
8
0
7
0
6
DELAY
0
5
0
4
3
0
0
2
0
1
2303
0
0