MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 362

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
362
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_IRQ
CMDCMPLT_
IRQ_EN
CH15_
CH14_
CH13_
CH12_
CH11_
CH10_
CH0_
CH9_
CH8_
CH7_
CH6_
CH5_
CH4_
CH3_
CH2_
Field
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Setting this bit enables the generation of an interrupt request for APBH DMA channel 0.
Interrupt request status bit for APBH DMA Channel 15. This sticky bit is set by DMA hardware and reset by
software. It is ANDed with its corresponding enable bit to generate an interrupt.
Interrupt request status bit for APBH DMA Channel 14. This sticky bit is set by DMA hardware and reset by
software. It is ANDed with its corresponding enable bit to generate an interrupt.
Interrupt request status bit for APBH DMA Channel 13. This sticky bit is set by DMA hardware and reset by
software. It is ANDed with its corresponding enable bit to generate an interrupt.
Interrupt request status bit for APBH DMA Channel 12. This sticky bit is set by DMA hardware and reset by
software. It is ANDed with its corresponding enable bit to generate an interrupt.
Interrupt request status bit for APBH DMA Channel 11. This sticky bit is set by DMA hardware and reset by
software. It is ANDed with its corresponding enable bit to generate an interrupt.
Interrupt request status bit for APBH DMA Channel 10. This sticky bit is set by DMA hardware and reset by
software. It is ANDed with its corresponding enable bit to generate an interrupt.
Interrupt request status bit for APBH DMA Channel 9. This sticky bit is set by DMA hardware and reset by
software. It is ANDed with its corresponding enable bit to generate an interrupt.
Interrupt request status bit for APBH DMA Channel 8. This sticky bit is set by DMA hardware and reset by
software. It is ANDed with its corresponding enable bit to generate an interrupt.
Interrupt request status bit for APBH DMA channel 7. This sticky bit is set by DMA hardware and reset by
software. It is ANDed with its corresponding enable bit to generate an interrupt.
Interrupt request status bit for APBH DMA channel 6. This sticky bit is set by DMA hardware and reset by
software. It is ANDed with its corresponding enable bit to generate an interrupt.
Interrupt request status bit for APBH DMA channel 5. This sticky bit is set by DMA hardware and reset by
software. It is ANDed with its corresponding enable bit to generate an interrupt.
Interrupt request status bit for APBH DMA channel 4. This sticky bit is set by DMA hardware and reset by
software. It is ANDed with its corresponding enable bit to generate an interrupt.
Interrupt request status bit for APBH DMA channel 3. This sticky bit is set by DMA hardware and reset by
software. It is ANDed with its corresponding enable bit to generate an interrupt.
Interrupt request status bit for APBH DMA channel 2. This sticky bit is set by DMA hardware and reset by
software. It is ANDed with its corresponding enable bit to generate an interrupt.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_APBH_CTRL1 field descriptions (continued)
Description
Freescale Semiconductor, Inc.