MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 507

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
8002_43C0
8002_43D0
8002_42F0
8002_4300
8002_4310
8002_4320
8002_4330
8002_4340
8002_4350
8002_4360
8002_4370
8002_4380
8002_4390
8002_43A0
8002_43B0
8002_43E0
8002_43F0
8002_4400
8002_4410
8002_4420
8002_4430
Absolute
address
(hex)
APBX DMA Channel 4 Buffer Address Register
(HW_APBX_CH4_BAR)
APBX DMA Channel 4 Semaphore Register
(HW_APBX_CH4_SEMA)
AHB to APBX DMA Channel 4 Debug Information
(HW_APBX_CH4_DEBUG1)
AHB to APBX DMA Channel 4 Debug Information
(HW_APBX_CH4_DEBUG2)
APBX DMA Channel 5 Current Command Address Register
(HW_APBX_CH5_CURCMDAR)
APBX DMA Channel 5 Next Command Address Register
(HW_APBX_CH5_NXTCMDAR)
APBX DMA Channel 5 Command Register
(HW_APBX_CH5_CMD)
APBX DMA Channel 5 Buffer Address Register
(HW_APBX_CH5_BAR)
APBX DMA Channel 5 Semaphore Register
(HW_APBX_CH5_SEMA)
AHB to APBX DMA Channel 5 Debug Information
(HW_APBX_CH5_DEBUG1)
AHB to APBX DMA Channel 5 Debug Information
(HW_APBX_CH5_DEBUG2)
APBX DMA Channel 6 Current Command Address Register
(HW_APBX_CH6_CURCMDAR)
APBX DMA Channel 6 Next Command Address Register
(HW_APBX_CH6_NXTCMDAR)
APBX DMA Channel 6 Command Register
(HW_APBX_CH6_CMD)
APBX DMA Channel 6 Buffer Address Register
(HW_APBX_CH6_BAR)
APBX DMA Channel 6 Semaphore Register
(HW_APBX_CH6_SEMA)
AHB to APBX DMA Channel 6 Debug Information
(HW_APBX_CH6_DEBUG1)
AHB to APBX DMA Channel 6 Debug Information
(HW_APBX_CH6_DEBUG2)
APBX DMA Channel 7 Current Command Address Register
(HW_APBX_CH7_CURCMDAR)
APBX DMA Channel 7 Next Command Address Register
(HW_APBX_CH7_NXTCMDAR)
APBX DMA Channel 7 Command Register
(HW_APBX_CH7_CMD)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_APBX memory map (continued)
Register name
Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA)
(in bits)
Width
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
00A0_0000h
00A0_0000h
00A0_0000h
Reset value
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
7.5.37/554
7.5.38/555
7.5.39/555
7.5.40/558
7.5.41/558
7.5.42/559
7.5.43/559
7.5.44/561
7.5.45/562
7.5.46/562
7.5.47/565
7.5.48/565
7.5.49/566
7.5.50/566
7.5.51/568
7.5.52/569
7.5.53/570
7.5.54/572
7.5.55/572
7.5.56/573
7.5.57/573
Section/
page
507