MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1418

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
19.4.64 Default First-Level Page Table Movable PTE Locator 14
This register is used by the DFLPT to set the location for MPTE14.
When using the hardware-based Default First-Level Page Table (DFLPT), program this
value to set the location for Movable PTE (MPTE14) to any of the 4096 sections.
Address:
Re-
1418
set
Bit
W
R
31
0
RSVD1
RSVD0
RSVD1
30 27
26 24
23 12
30 27
SPAN
Field
11 0
Field
LOC
DIS
DIS
31
31
30
0
RSVD1
29
0
HW_DIGCTL_MPTE14_LOC
(HW_DIGCTL_MPTE14_LOC)
28
0
Setting this bit to 1 disables the MPTE. A disabled MPTE cannot be bound to the page table and cannot be
modified.
Reserved.
This bit-field allows this PTE to span a larger than 1MB section of memory. Specifically 1MB * (2^SPAN).
Care must be taken to make sure that spanned regions do not overlap in the page table, since the DFLPT
does not provide any correction mechanism in an overlapped scenario. Because only one value can be set
for the MPTE base-address section entry, the DFLPT assumes linear physical 1 MB addressing within a
SPAN. For example, assuming a value N for LOC and SPAN=2, the DFLPT assumes the value of LOC,
LOC+1, LOC+2 and LOC+3 for the four values within that span; that is, all base addresses within a span
are contiguous.
Reserved.
Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT.Note that when the
SPAN field is used, any MPTE can cover up to 128MB. Do not program to 0x800 (fixed PIO entry). No two
HW_DIGCTL_MPTEn_LOC registers can have the same value, and care must be taken to not create overlap
when using the SPAN feature. Doing so will result in non-deterministic behavior of the DFLPT.
Setting this bit to 1 disables the MPTE. A disabled MPTE cannot be bound to the page table and cannot be
modified.
Reserved.
27
0
26
0
SPAN
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_DIGCTL_MPTE13_LOC field descriptions
HW_DIGCTL_MPTE14_LOC field descriptions
24
0
23
0
22
0
21
0
20
8001_C000h base + 5E0h offset = 8001_C5E0h
0
19
0
RSVD0
18
0
17
0
16
0
15
0
Description
Description
14
0
13
0
12
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
0
6
LOC
0
5
0
4
3
1
1
2
1
1
0
0