MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 480

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
6.5.105 AHB to APBH DMA Channel 13 Debug Information
This register gives debug visibility for the APB and AHB byte counts for DMA Channel
13.
This register allows debug visibility of the APBH DMA Channel 13.
480
STATEMACHINE
Field
4 0
(HW_APBH_CH13_DEBUG2)
HW_APBH_CH13_DEBUG1 field descriptions (continued)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
PIO Display of the DMA Channel 13 state machine state.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0C
0x0D
0x0E
0x0F
0x14
0x15
0x1C
0x1D
0x1E
0x1F
IDLE — This is the idle state of the DMA state machine.
REQ_CMD1 — State in which the DMA is waiting to receive the first word of a command.
REQ_CMD3 — State in which the DMA is waiting to receive the third word of a command.
REQ_CMD2 — State in which the DMA is waiting to receive the second word of a command.
XFER_DECODE — The state machine processes the descriptor command field in this state
and branches accordingly.
REQ_WAIT — The state machine waits in this state for the PIO APB cycles to complete.
REQ_CMD4 — State in which the DMA is waiting to receive the fourth word of a command,
or waiting to receive the PIO words when PIO count is greater than 1.
PIO_REQ — This state determines whether another PIO cycle needs to occur before starting
DMA transfers.
READ_FLUSH — During a read transfers, the state machine enters this state waiting for the
last bytes to be pushed out on the APB.
READ_WAIT — When an AHB read request occurs, the state machine waits in this state
for the AHB transfer to complete.
WRITE — During DMA Write transfers, the state machine waits in this state until the AHB
master arbiter accepts the request from this channel.
READ_REQ — During DMA Read transfers, the state machine waits in this state until the
AHB master arbiter accepts the request from this channel.
CHECK_CHAIN — Upon completion of the DMA transfers, this state checks the value of
the Chain bit and branches accordingly.
XFER_COMPLETE — The state machine goes to this state after the DMA transfers are
complete, and determines what step to take next.
TERMINATE — When a terminate signal is set, the state machine enters this state until the
current AHB transfer is completed.
WAIT_END — When the Wait for Command End bit is set, the state machine enters this
state until the DMA device indicates that the command is complete.
WRITE_WAIT — During DMA Write transfers, the state machine waits in this state until the
AHB master completes the write to the AHB memory space.
HALT_AFTER_TERM — If HALTONTERMINATE is set and a terminate signal is set, the
state machine enters this state and effectively halts. A channel reset is required to exit this
state
CHECK_WAIT — If the Chain bit is a 0, the state machine enters this state and effectively
halts.
WAIT_READY — When the NAND Wait for Ready bit is set, the state machine enters this
state until the GPMI device indicates that the external device is ready.
Description
Freescale Semiconductor, Inc.