MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 261

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MCIMX286CVM4B

Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r

Specifications of MCIMX286CVM4B

Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
5.4.85 Interrupt Collector Interrupt Register 75
This register provides a mechanism to specify the priority level for an interrupt source. It
also provides an enable and software interrupt for each one, as well as security designation.
HW_ICOLL_INTERRUPT75: 0x5D0
HW_ICOLL_INTERRUPT75_SET: 0x5D4
HW_ICOLL_INTERRUPT75_CLR: 0x5D8
HW_ICOLL_INTERRUPT75_TOG: 0x5DC
This register provides a mechanism to specify the priority associated with an interrupt bit.
In addition, this register controls the enable and software generated interrupt. WARNING:
Modifying the priority of an enabled interrupt may result in undefined behavior. You should
always disable an interrupt prior to changing its priority.
EXAMPLE
HW_ICOLL_INTERRUPT75_SET(0,0x00000001);
Address:
Freescale Semiconductor, Inc.
Reset
Reset
Bit
Bit
W
W
RSRVD1
R
R
ENFIQ
Field
31 5
4
31
15
0
0
(HW_ICOLL_INTERRUPT75)
HW_ICOLL_INTERRUPT75
05D0h
30
14
0
0
Always write zeroes to this bitfield.
Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through
the main IRQ FSM and priority logic.
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_ICOLL_INTERRUPT75 field descriptions
28
12
0
0
27
11
0
0
RSRVD1[15:5]
8000_0000h base + 5D0h offset = 8000_
26
10
0
0
25
0
0
9
RSRVD1[31:16]
24
0
0
8
Description
23
0
0
7
22
0
0
6
21
0
5
0
Chapter 5 Interrupt Collector (ICOLL)
20
0
4
0
19
0
0
3
18
0
0
2
PRIORITY
17
0
0
1
16
0
0
0
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