MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1607

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 26 Ethernet Controller (ENET)
26.3 Ethernet ENET-MAC Core
This section describes the ENET-MAC core, including the block diagram and formats.
26.3.1 Introduction
Ethernet is available in different speeds (10/100 Mbps) and provides connectivity to meet
a wide range of needs and from desktop to switches.
10GbEth
Access switch
1GbEth
Backone
switch
1GbEth
1GbEth
Work group
Work group
Switch
Switch
100MbEth
100MbEth
100MbEth
10MbEth
Desktop (Wiring Closet)
Figure 26-3. Enterprise LAN Topology Example
The ENET-MAC Core implements, in conjunction with a dual-speed 10/100 MAC, Layer
3 network acceleration functions, which are designed to accelerate the processing of various
common networking protocols such as IP, TCP, UDP and ICMP providing wire speed
services to Client applications.
The Core implements a dual speed 10/100 Mbps Ethernet MAC compliant with the
IEEE802.3-2002 standard. The MAC layer provides compatibility with Half or Full Duplex
10/100 Mbps Ethernet and Fast Ethernet LANs.
The MAC operation is fully programmable and can be used in NIC (Network Interface
Card), bridging or switching applications. The Core implements the Remote Network
Monitoring (RMON) counters according to IETF RFC 2819. All registers are accessible
through a 32-Bit APB interface.
The Core also implements a Hardware acceleration block to optimize the performance of
network controllers providing IP and TCP, UDP, ICMP protocol services. The acceleration
block performs, in hardware, critical functions, which are typically implemented with large
software overhead.
The Core implements programmable embedded FIFOs that can provide, on the Receive
path, buffering for loss-less flow control.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.
1607