MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1176

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
1176
ODT_RD_MAP_
ODT_RD_MAP_
ODT_RD_MAP_
RSVD3
RSVD2
RSVD1
23 20
19 16
15 12
11 8
Field
CS2
CS1
CS0
7 4
3 0
Bit [3] = CS3 will have active ODT termination when chip select X is performing a read.
Bit [2] = CS2 will have active ODT termination when chip select X is performing a read.
Bit [1] = CS1 will have active ODT termination when chip select X is performing a read.
Bit [0] = CS0 will have active ODT termination when chip select X is performing a read.
Etc.
Always write zeroes to this field.
Determines which chip(s) will have termination when a read occurs on chip 2.
Sets up which (if any) chip(s) will have their ODT termination active while a read occurs on chip select X.
EMI will define this parameter at default for internal testing. The user is required is to change this setting to
meet system specifications.
Example: If the system consists of 4 chip selects and odt_rd_map_cs0 is set to 'b0010, then when CS0 is
performing a read, CS1 will have active ODT termination. And if odt_rd_map_cs0 was set to 'b1000, then
instead CS3 would be active.
Bit [3] = CS3 will have active ODT termination when chip select X is performing a read.
Bit [2] = CS2 will have active ODT termination when chip select X is performing a read.
Bit [1] = CS1 will have active ODT termination when chip select X is performing a read.
Bit [0] = CS0 will have active ODT termination when chip select X is performing a read.
Etc.
Always write zeroes to this field.
Determines which chip(s) will have termination when a read occurs on chip 1.
Sets up which (if any) chip(s) will have their ODT termination active while a read occurs on chip select X.
EMI will define this parameter at default for internal testing. The user is required is to change this setting to
meet system specifications.
Example: If the system consists of 4 chip selects and odt_rd_map_cs0 is set to 'b0010, then when CS0 is
performing a read, CS1 will have active ODT termination. And if odt_rd_map_cs0 was set to 'b1000, then
instead CS3 would be active.
Bit [3] = CS3 will have active ODT termination when chip select X is performing a read.
Bit [2] = CS2 will have active ODT termination when chip select X is performing a read.
Bit [1] = CS1 will have active ODT termination when chip select X is performing a read.
Bit [0] = CS0 will have active ODT termination when chip select X is performing a read.
Etc.
Always write zeroes to this field.
Determines which chip(s) will have termination when a read occurs on chip 0.
Sets up which (if any) chip(s) will have their ODT termination active while a read occurs on chip select X.
EMI will define this parameter at default for internal testing. The user is required is to change this setting to
meet system specifications.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_DRAM_CTL83 field descriptions (continued)
Description
Freescale Semiconductor, Inc.