MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 855

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

10.8 Programmable Registers
CLKCTRL Hardware Register Format Summary
Freescale Semiconductor, Inc.
8004_00C0
8004_00D0
8004_0000
8004_0010
8004_0020
8004_0030
8004_0040
8004_0050
8004_0060
8004_0070
8004_0080
8004_0090
8004_00A0
8004_00B0
Absolute
address
(hex)
System PLL0, System/USB0 PLL Control Register 0
(HW_CLKCTRL_PLL0CTRL0)
System PLL0, System/USB0 PLL Control Register 1
(HW_CLKCTRL_PLL0CTRL1)
System PLL1, USB1 PLL Control Register 0
(HW_CLKCTRL_PLL1CTRL0)
System PLL1, USB1 PLL Control Register 1
(HW_CLKCTRL_PLL1CTRL1)
System PLL2, Ethernet PLL Control Register 0
(HW_CLKCTRL_PLL2CTRL0)
CPU Clock Control Register (HW_CLKCTRL_CPU)
AHB, APBH Bus Clock Control Register
(HW_CLKCTRL_HBUS)
APBX Clock Control Register (HW_CLKCTRL_XBUS)
XTAL Clock Control Register (HW_CLKCTRL_XTAL)
Synchronous Serial Port0 Clock Control Register
(HW_CLKCTRL_SSP0)
Synchronous Serial Port1 Clock Control Register
(HW_CLKCTRL_SSP1)
Synchronous Serial Port2 Clock Control Register
(HW_CLKCTRL_SSP2)
Synchronous Serial Port3 Clock Control Register
(HW_CLKCTRL_SSP3)
General-Purpose Media Interface Clock Control Register
(HW_CLKCTRL_GPMI)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_CLKCTRL_RESET_CHIP
HW_CLKCTRL_RESET_DIG
Figure 10-4. Reset Logic Functional Diagram
Register name
HW_CLKCTRL memory map
Reset sequence
clock control
signals
FSM
ENET_swi_reset_n
Chip_reset_n
Chapter 10 Clock Generation and Control (CLKCTRL)
Power_reset_n
(in bits)
Width
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Digital Domain
ENET
Power
DCDC
Chip
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value
0000_0000h
0000_0000h
8000_0000h
0000_0000h
8000_0000h
0001_0001h
0000_0001h
0000_0100h
6000_0001h
8000_0001h
8000_0001h
8000_0001h
8000_0001h
8000_0001h
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10.8.12/871
10.8.13/873
10.8.14/874
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