MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 45
MCIMX286CVM4B
Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(70 pages)
2.MCIMX283DVM4B.pdf
(2 pages)
3.MCIMX283DVM4B.pdf
(2327 pages)
4.MCIMX283DVM4B.pdf
(20 pages)
Specifications of MCIMX286CVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
3.4.9
The I
The following section describes I
Figure 25
(IC1–IC11) shown in the figure.
1
2
3
4
Freescale Semiconductor
I2C_SDA
I2C_SCL
A device must internally provide a hold time of at least 300 ns for the I2C_SDA signal in order to bridge the undefined region
of the falling edge of I2C_SCL.
The maximum IC4 has to be met only if the device does not stretch the LOW period (ID no IC5) of the I2C_SCL signal.
A fast-mode I2C bus device can be used in a standard-mode I
of 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the I2C_SCL signal.
If such a device does stretch the LOW period of the I2C_SCL signal, it must output the next data bit to the I2C_SDA line
max_rise_time (ID No IC9) + data_setup_time (ID No IC7) = 1000 + 250 = 1250 ns (according to the standard-mode I
specification) before the I2C_SCL line is released.
C
IC10
IC11
IC12
b
IC1
IC2
IC3
IC4
IC5
IC6
IC7
IC8
IC9
ID
= total capacitance of one bus line in pF.
2
C module is designed to support up to 400-Kbps I
shows the timing of the I
I2C_SCL cycle time
Hold time (repeated) START condition
Set-up time for STOP condition
Data hold time
HIGH Period of I2C_SCL clock
LOW Period of the I2C_SCL clock
Set-up time for a repeated START condition
Data set-up time
Bus free time between a STOP and START condition
Rise time of both I2C_SDA and I2C_SCL signals
Fall time of both I2C_SDA and I2C_SCL signals
Capacitive load for each bus line (C
Inter IC (I
IC2
START
i.MX28 Applications Processor Data Sheet for Consumer Products, Rev. 0
2
IC10
IC6
C) Timing
Table 49. I
IC8
IC1
Parameter
IC10
2
Figure 25. I
C SDA and SCL signal timings.
2
IC5
2
C module.
C Module Timing Parameters: 1.8 V
IC4
b
)
2
C Module Timing Diagram
IC11
Table 49
IC11
2
C bus system, but the requirement of Set-up time (ID No IC7)
2
describes the I
C connection compliant with I
IC7
START
Standard Mode
Min.
250
4.0
4.0
4.0
4.7
4.7
4.7
10
0
—
—
—
1
2
C module timing parameters
–
3.45
Max.
1000
300
400
3.6 V
—
—
—
—
—
—
—
—
2
IC3
20+0.1C
20+0.1C
STOP
Min.
100
2.5
0.6
0.6
0.6
1.3
0.6
1.3
0
—
Fast Mode
1
3
b
b
2
4
4
C bus protocol.
IC9
Max.
0.9
300
300
400
—
—
—
—
—
—
—
—
START
2
2
Unit
C bus
μs
μs
μs
μs
μs
μs
μs
ns
μs
ns
ns
pF
45