MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 7

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor
FlexCAN(2)
Mnemonic
CLKCTRL
ENET(2)
DIGCTL
DUART
DFLPT
Block
GPMI
BCH
DCP
EMI
BSI
ECC
accelerator
Scan Interface
Clock control
module
Data
co-processor
Default
first-level page
table
and on-chip
RAM
memory
interface
Controller
area network
module
General-pur-
pose media
interface
Bit-correcting
Boundary
Digital control
Debug UART Connectivity
External
Ethernet MAC
Controller
Block Name
i.MX28 Applications Processor Data Sheet for Consumer Products, Rev. 0
Table 4. i.MX28 Digital and Analog Modules (continued)
Connectivity
peripherals
Connectivity
peripherals
Clocks
Security
System control The DFLPT provides a unique method of implementing the ARM MMU
System control The digital control module includes sections on controlling the SRAM, the
peripherals
Connectivity
peripherals
Connectivity
peripherals
Connectivity
peripherals
Connectivity
peripherals
Subsystem
The Bose, Ray-Chaudhuri, Hocquenghem (BCH) Encoder and Decoder
module is capable of correcting from 2 to 20 single bit errors within a block of
data no larger than about 900 bytes (512 bytes is typical) in applications such
as protecting data and resources stored on modern NAND flash devices.
The boundary scan interface is provided to enable board level testing.
There are five pins on the device which is used to implement the IEEE Std
1149.1™ boundary scan protocol.
The clock control module, or CLKCTRL, generates the clock domains for all
components in the i.MX28 system. The crystal clock or PLL clock are the two
fundamental sources used to produce most of the clock domains. For lower
performance and reduced power consumption, the crystal clock is selected.
The PLL is selected for higher performance requirements but requires
increased power consumption. In most cases, when the PLL is used as the
source, a Phase Fractional Divider (PFD) can be programmed to reduce the
PLL clock frequency by up to a factor of 2.
This module provides support for general encryption and hashing functions
typically used for security functions. Because its basic job is moving data
from memory to memory, it also incorporates a memory-copy (memcopy)
function for both debugging and as a more efficient method of copying data
between memory blocks than the DMA-based approach.
first-level page table (L1PT) using a hardware-based approach.
performance monitors, high-entropy pseudo-random number seed,
free-running microseconds counter, and other chip control functions.
The Debug UART performs the following data conversions:
The i.MX28 supports off-chip DRAM storage through the EMI controller,
which is connected to the four internal AHB/AXI busses. The EMI supports
multiple external memory types, including:
Two Ethernet MAC controllers, each connected to one uDMA (unified DMA).
Supports 10/100 Mbps with TCP/UDP/IP Acceleration and IEEE 1588
Functions; also supports two RMII connectivity or one MII connectivity.
The Controller Area Network (CAN) protocol is a message based protocol
used for serial data. It was designed specifically for automotive but is also
used in industrial control and medical applications. The serial data bus runs
at 1 Mbps.
The General-Purpose Media Interface (GPMI) controller is a flexible NAND
flash controller with 8-bit data width, up to 50-MBps I/O speed and individual
chip select and DMA channels for up to 8 NAND devices. It also provides a
interface to 20-bit BCH for ECC.
• Serial-to-parallel conversion on data received from a peripheral device
• Parallel-to-serial conversion on data transmitted to the peripheral device
• 1.8-V Mobile DDR1 (LP-DDR1)
• Standard 1.8-V DDR2
• Low Voltage 1.5-V DDR2 (LV-DDR2)
Brief Description
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