S1D13743F00A200 Epson, S1D13743F00A200 Datasheet - Page 14

• Manufacturer Part Number: S1D13743F00A200
• Description: LCD Drivers LCD CNTRL w/Embedded 464KB SRAM
• Manufacturer: Epson

Specifications of S1D13743F00A200

• Maximum Clock Frequency: 33 MHz, 68.59 MHz
• Operating Supply Voltage: 1.5 V
• Maximum Operating Temperature: + 85 C
• Package / Case: QFP-20-144
• Attached Touch Screen: No
• Maximum Supply Current: 74 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Page 14
4.2.1 Intel 80 Host Interface
S1D13743
X70A-A-001-02
GPIO_INT
Pin Name
MD[15:0]
RESET#
D/C#
WE#
RD#
CS#
TE
Type
IO
O
O
I
I
I
I
I
B7, B6, B5,
B8, A9, A8,
A7, A6, A5,
B2, C3, C1
B10, B9,
FCBGA
B3, C2,
Pin #
C10
C8
C9
C7
D2
D3
D1
131,126,
124,102,
103,143,
141,136,
138,135,
132,127,
125,107,
108,106
Pin #
QFP
137
142
130
144
101
98
97
Table 4-1: Host Interface Pin Descriptions
Cell
HIS
HO
HO
HB
HI
HI
HI
HI
Voltage
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
Revision 2.7
IO
RESET#
State
Input
Input
Input
Input
Input
Hi-Z
L
L
Power
Status
Save
Input
Input
Input
Input
Input
Hi-Z
L
L
Intel 80 Host Data lines 15-0.
Note: The Host Data Lines can be swapped
(i.e. D15 = D0) using the CNF0 pin. For
details, see Section 4.3, “Summary of
Configuration Options” on page 18.
This input pin is the Write Enable signal.
This input pin is the Read Enable signal.
This input pin is the Chip Select signal.
This input pin selects between Intel 80 address
and data.
Tearing Effect: this pin will reflect the VSYNC,
HSYNC or the OR’d combination status of the
display.
This interrupt pin is associated with selected
GPIO pins when configured as inputs or
outputs. See Section 10.3.10, “General
Purpose IO Pins Registers” on page 71 for
operational description.
This active low input sets all internal registers
to the default state and forces all signals to
their inactive states.
Epson Research and Development
Hardware Functional Specification
Description
Vancouver Design Center
Issue Date: 2010/05/18