S1D13743F00A200 Epson, S1D13743F00A200 Datasheet - Page 43

• Manufacturer Part Number: S1D13743F00A200
• Description: LCD Drivers LCD CNTRL w/Embedded 464KB SRAM
• Manufacturer: Epson

Specifications of S1D13743F00A200

• Maximum Clock Frequency: 33 MHz, 68.59 MHz
• Operating Supply Voltage: 1.5 V
• Maximum Operating Temperature: + 85 C
• Package / Case: QFP-20-144
• Attached Touch Screen: No
• Maximum Supply Current: 74 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Epson Research and Development
Vancouver Design Center
9.4 Setting SYSCLK and PCLK
Hardware Functional Specification
Issue Date: 2010/05/18
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SysClk/7
The period of the system clock, TSYSCLK, must be set such that it falls within the
following range:
For PLL:
For CLKI:
where T
For example, if the minimum back-to-back cycle time of the Intel 80 Interface is 47.5ns,
then:
For PLL:
For CLKI:
Therefore,
For PLL:
For CLKI:
Care should be taken when setting T
can be achieved. PCLK is an integer divided version of SYSCLK. The following graph
shows the suggested setting for SYSCLK for a given value of PCLK for T
SysClk/6
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Figure 9-3: Setting of SYSCLK for a Desired PCLK
BBC
SysClk/5
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15.03ns < T
14.58ns < T
15.03ns < T
14.58ns < T
44.28MHz < f
42.99MHz < f
is the minimum back-to-back cycle time of the Intel 80 Interface.
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SysClk/4
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
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PCLK Frequency (MHz)
Revision 2.7
< (T
< (T
< 22.584ns
< 23.262ns
< 66.53MHz
< 68.59MHz
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BBC
BBC
SYSCLK
- 0.976) x 0.485ns
- 0.976) x 0.5ns
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so that the desired PCLK frequency, f
SysClk/3
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22
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SysClk/2
BBC
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X70A-A-001-02
= 47.5ns.
S1D13743
PCLK
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