S1D13743F00A200 Epson, S1D13743F00A200 Datasheet - Page 37

• Manufacturer Part Number: S1D13743F00A200
• Description: LCD Drivers LCD CNTRL w/Embedded 464KB SRAM
• Manufacturer: Epson

Specifications of S1D13743F00A200

• Maximum Clock Frequency: 33 MHz, 68.59 MHz
• Operating Supply Voltage: 1.5 V
• Maximum Operating Temperature: + 85 C
• Package / Case: QFP-20-144
• Attached Touch Screen: No
• Maximum Supply Current: 74 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Epson Research and Development
Vancouver Design Center
1. Ts
Hardware Functional Specification
Issue Date: 2010/05/18
Symbol
t10
t11
t12
t13
t14
t15
t16
t17
t18
t1
t2
t3
t4
t5
t6
t7
t8
t9
= pixel clock period
VS cycle time
VS pulse width low
VS falling edge to HS falling edge phase difference
HS cycle time
HS pulse width low
HS Falling edge to DE active
DE pulse width
DE falling edge to HS falling edge
PCLK period
PCLK pulse width low
PCLK pulse width high
HS setup to PCLK falling edge
DE to PCLK rising edge setup time
DE hold from PCLK rising edge
Data setup to PCLK rising edge
Data hold from PCLK rising edge
DE Stop setup to VS start
Vertical Non-Display Period
Note
In 24-bit mode, the data is always guaranteed to be launched on the correct edge of
PCLK. In this mode, the frequency of PCLK is ½ the programmed internal value. If it is
desired that HS and VS are always launched on the same edge of PCLK as the data, then
HNDP, HSW, and HSS should be programmed with even values.
Parameter
Table 7-9: 18/24-Bit TFT A.C. Timing
Revision 2.7
Min
0.5
0.5
0.5
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
1
VDISP + VNDP
HDISP + HNDP
HNDP-HPS
HDISP
VNDP
HSW
VSW
HPS
HPS
VPS
Typ
—
—
—
—
—
—
—
—
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X70A-A-001-02
Units
Lines
Lines
S1D13743
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
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