S1D13743F00A200 Epson, S1D13743F00A200 Datasheet - Page 53

LCD Drivers LCD CNTRL w/Embedded 464KB SRAM

S1D13743F00A200

Manufacturer Part Number
S1D13743F00A200
Description
LCD Drivers LCD CNTRL w/Embedded 464KB SRAM
Manufacturer
Epson
Datasheet

Specifications of S1D13743F00A200

Maximum Clock Frequency
33 MHz, 68.59 MHz
Operating Supply Voltage
1.5 V
Maximum Operating Temperature
+ 85 C
Package / Case
QFP-20-144
Attached Touch Screen
No
Maximum Supply Current
74 mA
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S1D13743F00A200
Manufacturer:
EPSON
Quantity:
5 690
Epson Research and Development
Vancouver Design Center
REG[1Ch] bits 1-0
REG[1Ah] bits 7-0
bits 7-0
bit 7
bits 6-0
Hardware Functional Specification
Issue Date: 2010/05/18
REG[1Ah] Vertical Display Height Register 0 (VDISP)
Default = 01h
REG[1Ch] Vertical Display Height Register 1 (VDISP)
Default = 00h
REG[1Eh] Vertical Non-Display Period Register (VNDP)
Default = 01h
REG[20h] HS Pulse Width Register (HSW)
Default = 00h
HS Pulse Polarity
7
7
7
7
6
6
6
6
Note
Note
Vertical Display Height bits [9:0]
These bits specify the Vertical Display Height (VDISP) for the LCD panel, in lines.
Vertical Non-Display Period bits [7:0]
These bits specify the Vertical Non-Display Period (VNDP) for the LCD panel, in lines.
HS Pulse Polarity
This bit selects the polarity of the horizontal sync signal. This bit is set according to the
horizontal sync signal of the panel.
When this bit = 0, the horizontal sync signal is active low.
When this bit = 1, the horizontal sync signal is active high.
HS Pulse Width bits [6:0]
These bits specify the width of the horizontal sync signal for the LCD panel (HSW), in
pixels. The horizontal sync signal is typically HS, depending on the panel type.
The minimum Vertical Display Height is 1 line
(REG[1Ch] bits 1-0, REG[1Ah] bits 7-0 = 001h).
The minimum Vertical Non-Display Period is 2 lines (REG[1Eh] bits 7-0 = 02h).
VDISP in lines = (REG[1Ch] bits 1-0, REG[1Ah] bits 7-0)
VNDP in lines = REG[1Eh] bits 7-0
HSW in pixels = REG[20h] bits 6-0
5
5
5
5
n/a
Vertical Non-Display Period bits 7-0
Vertical Display Height bits 7-0
4
4
4
4
Revision 2.7
HS Pulse Width bits 6-0
3
3
3
3
2
2
2
2
Vertical Display Height bits 9-8
1
1
1
1
Read/Write
Read/Write
Read/Write
Read/Write
X70A-A-001-02
S1D13743
0
0
0
0
Page 53

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