S1D13743F00A200 Epson, S1D13743F00A200 Datasheet - Page 50

• Manufacturer Part Number: S1D13743F00A200
• Description: LCD Drivers LCD CNTRL w/Embedded 464KB SRAM
• Manufacturer: Epson

Specifications of S1D13743F00A200

• Maximum Clock Frequency: 33 MHz, 68.59 MHz
• Operating Supply Voltage: 1.5 V
• Maximum Operating Temperature: + 85 C
• Package / Case: QFP-20-144
• Attached Touch Screen: No
• Maximum Supply Current: 74 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Page 50
bits 7-3
S1D13743
X70A-A-001-02
REG[12h] Clock Source Select Register
Default = 00h
REG[12h] bits 7-3
7
00000b
00001b
00010b
00011b
00100b
00101b
00110b
00111b
01000b
01001b
01010b
01011b
01100b
01101b
01110b
01111b
6
PCLK Divide Select bits [4:0]
These bits specify the divide ratio for the panel clock (PCLK) frequency.
The clock source for PCLK is SYSCLK.
All resulting clock frequencies will maintain a 50/50 duty cycle regardless of divide ratio.
PCLK Divide Select bits 4-0
PCLK Divide Ratio
5
Table 10-4 PCLK Divide Ratio Selection
Reserved
10:1
11:1
12:1
13:1
14:1
15:1
16:1
2:1
3:1
4:1
5:1
6:1
7:1
8:1
9:1
4
Revision 2.7
3
REG[12h] bits 7-3
10000b
10001b
10010b
10011b
10100b
10101b
10110b
10111b
11000b
11001b
11010b
11011b
11100b
11101b
11110b
11111b
2
Epson Research and Development
n/a
Hardware Functional Specification
PCLK Divide Ratio
1
Vancouver Design Center
Issue Date: 2010/05/18
17:1
18:1
19:1
20:1
21:1
22:1
23:1
24:1
25:1
26:1
27:1
28:1
29:1
30:1
31:1
32:1
Read/Write
SYSCLK Source
Select
0