S1D13743F00A200 Epson, S1D13743F00A200 Datasheet - Page 45

• Manufacturer Part Number: S1D13743F00A200
• Description: LCD Drivers LCD CNTRL w/Embedded 464KB SRAM
• Manufacturer: Epson

Specifications of S1D13743F00A200

• Maximum Clock Frequency: 33 MHz, 68.59 MHz
• Operating Supply Voltage: 1.5 V
• Maximum Operating Temperature: + 85 C
• Package / Case: QFP-20-144
• Attached Touch Screen: No
• Maximum Supply Current: 74 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Epson Research and Development
Vancouver Design Center
10.2 Register Set
REG[00h] Revision Code Register
REG[04h] PLL M-Divider Register
REG[08h] PLL Setting Register 1
REG[0Ch] PLL Setting Register 3
REG[10h]
REG[14h] Panel Type Register
REG[18h] Horizontal Non-Display Period Register (HNDP)
REG[1Ch] Vertical Display Height Register 1 (VDISP)
REG[20h] HS Pulse Width Register (HSW)
REG[24h] VS Pulse Width Register (VSW)
REG[28h] PCLK Polarity Register
REG[2Ah] Input Mode Register
REG[2Eh] Input YUV/RGB Translate Mode Register 1
REG[32h] V Data Fix Register
REG[34h] Display Mode Register
REG[38h] Window X Start Position Register 0
REG[3Ch] Window Y Start Position Register 0
REG[40h] Window X End Position Register 0
REG[44h] Window Y End Position Register 0
REG[48h] Memory Data Port Register 0
REG[4Ah] Memory Read Address Register 0
REG[4Eh] Memory Read Address Register 2
REG[50h] Gamma Correction Enable Register
REG[54h] Gamma Correction Table Data Register
REG[56h] Power Save Register
REG[5Ah] General Purpose IO Pins Configuration Register 0
REG[5Eh] GPIO Positive Edge Interrupt Trigger Register
REG[62h] GPIO Interrupt Status Register
Hardware Functional Specification
Issue Date: 2010/05/18
Register
The S1D13743 registers are listed in the following table.
Table 10-1: S1D13743 Register Set
Read-Only Configuration Registers
General Purpose IO Pins Registers
Clock Configuration Registers
Panel Configuration Registers
Gamma Correction Registers
Miscellaneous Registers
Display Mode Registers
Input Mode Register
Window Settings
Memory Access
Pg
Revision 2.7
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47
48
49
49
52
52
53
53
54
54
55
57
58
59
63
63
64
64
65
66
67
68
69
71
71
72
66
REG[02h] Configuration Readback Register
REG[06h] PLL Setting Register 0
REG[0Ah] PLL Setting Register 2
REG[0Eh] PLL Setting Register 4
REG[12h] Clock Source Select Register
REG[16h] Horizontal Display Width Register (HDISP)
REG[1Eh] Vertical Non-Display Period Register (VNDP)
REG[22h] HS Pulse Start Position Register (HPS)
REG[26h] VS Pulse Start Position Register (VPS)
REG[2Ch] Input YUV/RGB Translate Mode Register 0
REG[36h] Special Effects Register
REG[3Ah] Window X Start Position Register 1
REG[3Eh] Window Y Start Position Register 1
REG[42h] Window X End Position Register 1
REG[46h] Window Y End Position Register 1
REG[49h] Memory Data Port Register 1
REG[52h] Gamma Correction Table Index Register
REG[58h] Non-Display Period Control / Status Register
REG[5Ch] General Purpose IO Pins Status/Control Register 0
REG[64h] GPIO Pull-down Control Register
REG[1Ah] Vertical Display Height Register 0 (VDISP)
REG[30h] U Data Fix Register
REG[4Ch] Memory Read Address Register 1
REG[60h] GPIO Negative Edge Interrupt Trigger Register
Register
X70A-A-001-02
S1D13743
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