LAN8710A-EZK-TR SMSC, LAN8710A-EZK-TR Datasheet - Page 32

• Manufacturer Part Number: LAN8710A-EZK-TR
• Description: Ethernet ICs 10/100 Ethernet XCVR w/HPAutoMDIX FlexPwr
• Manufacturer: SMSC
• Type: Single Chipr

Specifications of LAN8710A-EZK-TR

• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 125 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.6 V or 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.2 (11-10-10)
3.5
MDIO
MDIO
MDC
MDC
Preamble
Preamble
32 1's
32 1's
The Serial Management Interface is used to control the device and obtain its status. This interface
supports registers 0 through 6 as required by Clause 22 of the 802.3 standard, as well as “vendor-
specific” registers 16 to 31 allowed by the specification. Non-supported registers (such as 7 to 15) will
be read as hexadecimal “FFFF”. Device registers are detailed in
on page
At the system level, SMI provides 2 signals: MDIO and MDC. The MDC signal is an aperiodic clock
provided by the station management controller (SMC). MDIO is a bi-directional data SMI input/output
signal that receives serial data (commands) from the controller SMC and sends serial data (status) to
the SMC. The minimum time between edges of the MDC is 160 ns. There is no maximum time
between edges. The minimum cycle time (time between two consecutive rising or two consecutive
falling edges) is 400 ns. These modest timing requirements allow this interface to be easily driven by
the I/O port of a microcontroller.
The data on the MDIO line is latched on the rising edge of the MDC. The frame structure and timing
of the data is shown in
further described in
Serial Management Interface (SMI)
Start of
Start of
0
Frame
0
Frame
48.
1
1
Figure 3.6 MDIO Timing and Frame Structure - WRITE Cycle
Figure 3.5 MDIO Timing and Frame Structure - READ Cycle
1
0
Code
Code
OP
OP
0
1
Section 5.5.6, "SMI Timing," on page
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
Figure 3.5
PHY Address
PHY Address
Data To Phy
Write Cycle
Read Cycle
DATASHEET
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR
and
Data To Phy
Figure
32
Register Address
Register Address
3.6. The timing relationships of the MDIO signals are
75.
Around
Around
Turn
Turn
Chapter 4, "Register Descriptions,"
D15
D15
D14
D14
SMSC LAN8710A/LAN8710Ai
Data From Phy
Data
Data
...
...
...
...
D1
D1
Datasheet
®
D0
D0
Technology