LAN8710A-EZK-TR SMSC, LAN8710A-EZK-TR Datasheet - Page 41

• Manufacturer Part Number: LAN8710A-EZK-TR
• Description: Ethernet ICs 10/100 Ethernet XCVR w/HPAutoMDIX FlexPwr
• Manufacturer: SMSC
• Type: Single Chipr

Specifications of LAN8710A-EZK-TR

• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 125 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.6 V or 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR
Datasheet
SMSC LAN8710A/LAN8710Ai
3.8.7
3.8.8
3.8.9
3.8.9.1
Ethernet
10/100
MAC
Collision Detect
A collision is the occurrence of simultaneous transmit and receive operations. The COL output is
asserted to indicate that a collision has been detected. COL remains active for the duration of the
collision. COL is changed asynchronously to both RXCLK and TXCLK. The COL output becomes
inactive during full duplex mode.
The COL may be tested by setting the
enables the collision test. COL will be asserted within 512 bit times of TXEN rising and will be de-
asserted within 4 bit times of TXEN falling.
Link Integrity Test
The device performs the link integrity test as outlined in the IEEE 802.3u (Clause 24-15) Link Monitor
state diagram. The link status is multiplexed with the 10Mbps link status to form the
the
The DSP indicates a valid MLT-3 waveform present on the RXP and RXN signals as defined by the
ANSI X3.263 TP-PMD standard, to the Link Monitor state-machine, using the internal DATA_VALID
signal. When DATA_VALID is asserted, the control logic moves into a Link-Ready state and waits for
an enable from the auto-negotiation block. When received, the Link-Up state is entered, and the
Transmit and Receive logic blocks become active. Should auto-negotiation be disabled, the link
integrity logic moves immediately to the Link-Up state when the DATA_VALID is asserted.
To allow the line to stabilize, the link integrity logic will wait a minimum of 330 μsec from the time
DATA_VALID is asserted until the Link-Ready state is entered. Should the DATA_VALID input be
negated at any time, this logic will immediately negate the Link signal and enter the Link-Down state.
When the 10/100 digital block is in 10BASE-T mode, the link status is derived from the 10BASE-T
receiver logic.
Loopback Operation
The device may be configured for near-end loopback and far loopback. These loopback modes are
detailed in the following subsections.
Near-end Loopback
Near-end loopback mode sends the digital transmit data back out the receive data signals for testing
purposes, as indicated by the blue arrows in
setting the
is operational in near-end loopback mode because data is routed through the PCS and PMA layers
into the PMD sublayer before it is looped back. The COL signal will be inactive in this mode, unless
Collision Test
of the state of TXEN.
Basic Status Register
TXD
Loopback
RXD
is enabled in the
Figure 3.9 Near-end Loopback Block Diagram
Digital
bit of the
Ethernet Transceiver
and to drive the LINK LED (LED1).
SMSC
Basic Control Register
Basic Control
DATASHEET
Analog
Collision Test
41
®
Technology
Register. The transmitters are powered down regardless
Figure
X
X
3.9. The near-end loopback mode is enabled by
to “1”. A large percentage of the digital circuitry
bit of the
TX
RX
Basic Control Register
XFMR
Revision 1.2 (11-10-10)
CAT-5
Link Status
to “1”. This
bit in