LAN8710A-EZK-TR SMSC, LAN8710A-EZK-TR Datasheet - Page 40

• Manufacturer Part Number: LAN8710A-EZK-TR
• Description: Ethernet ICs 10/100 Ethernet XCVR w/HPAutoMDIX FlexPwr
• Manufacturer: SMSC
• Type: Single Chipr

Specifications of LAN8710A-EZK-TR

• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 125 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.6 V or 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.2 (11-10-10)
3.8.4
3.8.5
3.8.5.1
3.8.5.2
3.8.6
state prior to power-down and asserts the nINT interrupt if the ENERGYON interrupt is enabled in the
Interrupt Mask
When the
disabled.
Isolate Mode
The device data paths may be electrically isolated from the MII/RMII interface by setting the
of the
TXEN and TXER inputs, but does respond to management transactions.
Isolation provides a means for multiple transceivers to be connected to the same MII/RMII interface
without contention. By default, the transceiver is not isolated (on power-up (Isolate=0).
Resets
The device provides two forms of reset: Hardware and Software. The device registers are reset by
both Hardware and Software resets. Select register bits, indicated as “NASR” in the register definitions,
are not cleared by a Software reset. The registers are not reset by the power-down modes described
in
Note: For the first 16us after coming out of reset, the MII/RMII interface will run at 2.5 MHz. After this
Hardware Reset
A Hardware reset is asserted by driving the nRST input pin low. When driven, nRST should be held
low for the minimum time detailed in
on page 70
supplied to the XTAL1/CLKIN signal.
Note: A hardware reset (nRST assertion) is required following power-up. Refer to
Software Reset
A Software reset is activated by setting the
registers bits, except those indicated as “NASR” in the register definitions, are cleared by a Software
reset. The
process will be completed within 0.5s from the setting of this bit.
Carrier Sense
The carrier sense (CRS) is output on the CRS pin in MII mode, and the CRS_DV pin in RMII mode.
CRS is a signal defined by the MII specification in the IEEE 802.3u standard. The device asserts CRS
based only on receive activity whenever the transceiver is either in repeater mode or full-duplex mode.
Otherwise the transceiver asserts CRS based on either transmit or receive activity.
The carrier sense logic uses the encoded, unscrambled data to determine carrier activity status. It
activates carrier sense with the detection of 2 non-contiguous zeros within any 10 bit span. Carrier
sense terminates if a span of 10 consecutive ones is detected before a /J/K/ Start-of Stream Delimiter
pair. If an SSD pair is detected, carrier sense is asserted until either /T/R/ End–of-Stream Delimiter
pair or a pair of IDLE symbols is detected. Carrier is negated after the /T/ symbol or the first IDLE. If
/T/ is not followed by /R/, then carrier is maintained. Carrier is treated similarly for IDLE followed by
some non-IDLE symbol.
Section
Basic Control Register
time, it will switch to 25 MHz if auto-negotiation is enabled.
"Power-On nRST & Configuration Strap Timing," on page 70
EDPWRDOWN
3.8.3.
Soft Reset
to ensure a proper transceiver reset. During a Hardware reset, an external clock must be
Register. The first and possibly the second packet to activate ENERGYON may be lost.
bit is self-clearing. Per the IEEE 802.3u standard, clause 22 (22.2.4.1.1) the reset
bit of the
to “1”. In isolation mode, the transceiver does not respond to the TXD,
DATASHEET
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR
Mode Control/Status Register
Section 5.5.3, "Power-On nRST & Configuration Strap Timing,"
40
Soft Reset
bit of the
is low, energy detect power-down is
Basic Control Register
for additional information.
SMSC LAN8710A/LAN8710Ai
Section 5.5.3,
to “1”. All
Isolate
Datasheet
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Technology
bit