A3P1000L-PQG208 Actel, A3P1000L-PQG208 Datasheet - Page 18

• Manufacturer Part Number: A3P1000L-PQG208
• Description: FPGA - Field Programmable Gate Array 1M SYSTEM GATES
• Manufacturer: Actel

Specifications of A3P1000L-PQG208

• Processor Series: A3P1000
• Core: IP Core
• Maximum Operating Frequency: 781.25 MHz
• Number Of Programmable I/os: 154
• Data Ram Size: 147456
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 1 M
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ProASIC3L DC and Switching Characteristics
Figure 2-1 • V5 Devices – I/O State as a Function of VCCI and VCC Voltage Levels
2 - 4
Deactivation trip point:
V
V
Activation trip point:
a
d
= 0.85 V ± 0.25 V
= 0.75 V ± 0.25 V
VCC = 1.575 V
VCC = 1.425 V
PLL Behavior at Brownout Condition
Actel recommends using monotonic power supplies or voltage regulators to ensure proper powerup
behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout
activation levels. The VCC activation level is specified as 1.1 V worst-case (see
2 on page 2-5
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25
V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down
Behavior of Low-Power Flash Devices" chapter of the
information on clock and lock recovery.
Internal Power-Up Activation Sequence
Output buffers, after 200 ns delay from input buffer activation.
VCC
1. Core
2. Input buffers
Region 1: I/O Buffers are OFF
for more details).
VCC = VCCI + VT
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
Deactivation trip point:
Activation trip point:
V
V
a
d
= 0.9 V ± 0.3 V
= 0.8 V ± 0.3 V
Region 1: I/O buffers are OFF
Region 2: I/O buffers are ON.
I/Os are functional (except differential inputs)
but slower because VCCI / VCC are below
specification. For the same reason, input
buffers do not meet VIH / VIL levels, and
output buffers do not meet VOH / VOL levels.
buffers do not meet VOH / VOL levels.
meet VIH / VIL levels, and output
same reason, input buffers do not
is below specification. For the
but slower because VCCI
(except differential
I/Os are functional
R e vi s i o n 9
buffers are ON.
Region 4: I/O
Min VCCI datasheet specification
standard; i.e., 1.425 V or 1.7 V
voltage at a selected I/O
or 2.3 V or 3.0 V
ProASIC3L FPGA Fabric User’s Guide
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
speed, VIH / VIL, VOH / VOL,
etc.
Region 5: I/O buffers are ON
and power supplies are within
specification.
I/Os meet the entire datasheet
and timer specifications for
Figure 2-1
and
VCCI
Figure 2-
for