A3P1000L-PQG208 Actel, A3P1000L-PQG208 Datasheet - Page 39
A3P1000L-PQG208
Manufacturer Part Number
A3P1000L-PQG208
Description
FPGA - Field Programmable Gate Array 1M SYSTEM GATES
Manufacturer
Actel
Datasheet
1.A3P250L-VQG100.pdf
(224 pages)
Specifications of A3P1000L-PQG208
Processor Series
A3P1000
Core
IP Core
Maximum Operating Frequency
781.25 MHz
Number Of Programmable I/os
154
Data Ram Size
147456
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
1 M
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P1000L-PQG208
Manufacturer:
Microsemi SoC
Quantity:
10 000
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Table 2-26 • Summary of AC Memory Points
Table 2-27 • I/O AC Parameter Definitions
Standard
3.3 V LVTTL /
3.3 V LVCMOS
3.3 V LVCMOS Wide
Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS
3.3 V PCI
3.3 V PCI-X
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
LVDS
LVPECL
Parameter
t
t
t
t
t
t
t
t
t
t
t
DP
PY
DOUT
EOUT
DIN
HZ
ZH
LZ
ZL
ZHS
ZLS
Summary of I/O Timing Characteristics – Default I/O Software
Settings
Data to Pad delay through the Output Buffer
Pad to Data delay through the Input Buffer
Data to Output Buffer delay through the I/O interface
Enable to Output Buffer Tristate Control delay through the I/O interface
Input Buffer to Data delay through the I/O interface
Enable to Pad delay through the Output Buffer—High to Z
Enable to Pad delay through the Output Buffer—Z to High
Enable to Pad delay through the Output Buffer—Low to Z
Enable to Pad delay through the Output Buffer—Z to Low
Enable to Pad delay through the Output Buffer with delayed enable—Z to High
Enable to Pad delay through the Output Buffer with delayed enable—Z to Low
Input Reference Voltage
(V
REF_TYP
0.75 V
0.75 V
1.25 V
1.25 V
0.8 V
0.8 V
1.0 V
1.0 V
1.5 V
1.5 V
–
–
–
–
–
–
–
–
–
–
)
Parameter Definition
R e v i s i o n 9
Board Termination
Voltage (V
1.485 V
1.485 V
0.75 V
0.75 V
1.25 V
1.25 V
1.2 V
1.2 V
1.5 V
1.5 V
–
–
–
–
–
–
–
–
–
–
TT_REF
)
ProASIC3L Low Power Flash FPGAs
Measuring Trip Point
0.615 * VCCI (FF))
0.285 * VCCI (RR)
0.285 * VCCI (RR)
0.615 * VCCI (FF)
Cross point
Cross point
(V
0.90 V
0.75 V
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
0.6 V
1.4 V
1.4 V
1.2 V
trip
)
2- 25
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