A3P1000L-PQG208 Actel, A3P1000L-PQG208 Datasheet - Page 219

• Manufacturer Part Number: A3P1000L-PQG208
• Description: FPGA - Field Programmable Gate Array 1M SYSTEM GATES
• Manufacturer: Actel

Specifications of A3P1000L-PQG208

• Processor Series: A3P1000
• Core: IP Core
• Maximum Operating Frequency: 781.25 MHz
• Number Of Programmable I/os: 154
• Data Ram Size: 147456
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 1 M
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4 – Datasheet Information
List of Changes
Revision
July 2010
Revision 9 (Feb 2009)
Product Brief v1.3
Revision 8 (Feb 2009)
Product Brief v1.2
Revision 7 (Aug 2008)
DC and Switching
Characteristics
Advance v0.6
Revision 6 (Aug 2008)
DC and Switching
Characteristics
Advance v0.5
The following table lists critical changes that were made in each revision of the ProASIC3L datasheet.
The versioning system for datasheets has been changed. Datasheets are
assigned a revision number that increments each time the datasheet is revised.
The
device in the device family.
The
I/O pairs for A3PE3000L from 300 to 310.
Table 2 • ProASIC3L FPGAs Package Sizes Dimensions
The
bullets regarding wide range power supply voltage support.
Advanced I/O Standards"
3.0 V LVCMOS wide range support data was added to
Operating Conditions
3.3 V LVCMOS wide range support data was added to
Maximum and Minimum DC Input and Output Levels Applicable to Commercial
and Industrial Conditions—Software Default Settings
Maximum and Minimum DC Input and Output Levels Applicable to Commercial
and Industrial Conditions—Software Default
3.3 V LVCMOS wide range support data was added to
AC Memory
3.3 V LVCMOS wide range support text was added to the
LVCMOS"
Table 2-48 • Minimum and Maximum DC Input and Output Levels for LVCMOS
3.3 V Wide Range
Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays
updated to add several new rows of values.
Table 2-7 • Quiescent Supply Current (I
Flash*Freeze Mode*
ProASIC3L Flash*Freeze Mode1
Table 2-18 • Different Components Contributing to Dynamic Power Consumption
in ProASIC3L Devices at 1.5 V VCC
Table 2-19 • Different Components Contributing to the Static Power Consumption
in ProASIC3L Devices
core operation.
Timing tables were updated to include tables for 1.5 V core voltage.
3.0 V wide range was added to the list of supported voltages in the
"I/Os Per Package
"ProASIC3L Device Status" table on page III
"Advanced and Pro (Professional) I/Os"
section.
Points.
is new.
1
through
.
1
was updated to add the static PLL contribution at 1.5 V
"
section. The
table was revised to change the number of differential
Table 2-10 • Quiescent Supply Current (I
were updated to add 1.5 V core voltage.
R e v i s i o n 9
Changes
is new.
"Wide Range I/O Support" section
Settings.
DD
section was revised to add two
) Characteristics, ProASIC3L
indicates the status for each
to
Table 2-2 • Recommended
Table 2-22 • Summary of
Table 2-26 • Summary of
Table 2-24 • Summary of
is new.
"3.3 V LVTTL / 3.3 V
"I/Os with
DD
is new.
), No
was
2-7
2-22
Page
2-23
2-25
2-39
2-40
2-14
2-14
N/A
N/A
1-7
2-2
2-7
to
II
II
I
2-8
to
4 -1