ML610Q429-NNNTBZ03A7 Rohm Semiconductor, ML610Q429-NNNTBZ03A7 Datasheet - Page 132

• Manufacturer Part Number: ML610Q429-NNNTBZ03A7
• Description: MCU 8BIT 48K FLASH 128-TQFP
• Manufacturer: Rohm Semiconductor

Specifications of ML610Q429-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 4.2MHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.3
The timer counters (TMnC) are set to an operating state (TnSTAT are set to “1”) on the first falling edge of the timer
clocks (TnCK) that are selected by the Timer 0 to 1 control register 0 (TMnCON0) when the TnRUN bits of timer 0 to
1control register 1 (TMnCON1) are set to “1” and increment the count value on the 2nd falling.
When the count value of TM0C to TM1C and the timer 0 to 1 data register (TMnD) coincide, timer 0 to 1 interrupt
(TMnINT) occurs on the next timer clock falling edge, TMnC are reset to “00H” and incremental counting continues.
When the TnRUN bits are set to “0”, TMnC stop counting after counting once the falling of the timer clock (TnCK).
Confirm that TMnC has been stopped by checking that the TnSTAT bit of the Timer 0–1 control register 1
(TMnCON1) is “0”. When the TnRUN bits are set to “1” again, TMn restart incremental counting from the previous
values. To initialize TMnC to “00H”, perform write operation in TMnC.
The timer interrupt period (TTMI) is expressed by the following equation.
TMnD:
TnCK:
After the TnRUN bits are set to “1”, timers are synchronized by the timer clock and counting starts so that an error of a
maximum of 1 clock period occurs until the first timer interrupt. The timer interrupt periods from the second time are
constant.
Figure 9-2 shows the normal timer mode operation timing diagram of Timer 0 to 1.
Note:
Even if “0” is written to the TnRUN bits, counting operation continues up to the falling edge (the timer 0 to 1 status
flag (TnSTA) is in a “1” state) of the next timer clock pulse. Therefore, the timer 0 to 1 interrupt (TMnINT) may
occur.
Write TMnC
TTMI =
Description of Operation
(n = 0 to 1)
Timer 0 to 1 data register (TMnD) setting value (01H to 0FFH)
Clock frequency selected by the Timer 0 to 1 control register 0 (TMnCON0)
TnSTAT
TMnINT
TnRUN
TMnC
TMnD
TnCK
Figure 9-2 Normal Timer Mode Operation Timing Diagram of Timer 0 to 1
XX
TnCK (Hz)
TMnD + 1
00
88
(n = 0 to 1)
01
T
TMI
02
9 – 12
87
88
88
00
ML610Q428/ML610Q429 User’s Manual
01
5F
60
Chapter 9 Timers
88
61
62