ML610Q429-NNNTBZ03A7 Rohm Semiconductor, ML610Q429-NNNTBZ03A7 Datasheet - Page 93
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ML610Q429-NNNTBZ03A7
Manufacturer Part Number
ML610Q429-NNNTBZ03A7
Description
MCU 8BIT 48K FLASH 128-TQFP
Manufacturer
Rohm Semiconductor
Datasheets
1.ML610Q482P-NNNTB03A7.pdf
(20 pages)
2.ML610Q428-NNNTBZ03A7.pdf
(32 pages)
3.ML610Q428-NNNTBZ03A7.pdf
(434 pages)
Specifications of ML610Q429-NNNTBZ03A7
Core Processor
nX-U8/100
Core Size
8-Bit
Speed
4.2MHz
Connectivity
I²C, SSP, UART/USART
Peripherals
LCD, Melody Driver, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 2x12b, 2x24b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ML610Q429-NNNTBZ03A7
Manufacturer:
Rohm
Quantity:
900
Company:
Part Number:
ML610Q429-NNNTBZ03A7
Manufacturer:
Rohm Semiconductor
Quantity:
10 000
- ML610Q482P-NNNTB03A7 PDF datasheet
- ML610Q428-NNNTBZ03A7 PDF datasheet #2
- ML610Q428-NNNTBZ03A7 PDF datasheet #3
- Current page: 93 of 434
- Download datasheet (3Mb)
Reset of voltage regulator
for low-speed oscillation
6.3.1.2
The low-speed clock generation circuit is activated by the occurrence of power ON reset.
A low-speed clock (LSCLK) is supplied to the peripheral circuits after the elapse of the low-speed oscillation start
period (T
The low-speed clock generation circuit stops the oscillation in STOP mode. When oscillation is resumed by releasing
of the STOP mode by external interrupt, LSCLK is supplied to the peripheral circuits after the elapse of the low-speed
oscillation start period (T
Chapter 4, “MCU Control Function”.
Figure 6-3 shows the waveforms of the low-speed clock generation circuit. For the low-speed oscillation start time
(T
Note:
After the power supply is turned on, CPU starts operation with a high-speed clock (500 kHz RC oscillation). It is
recommended to switch to the low-speed clock after confirming that the low-speed clock is oscillating by checking that
the 128 Hz interrupt request bit (Q128H) of the low-speed time base counter is “1”. If the clock is switched before the
low-speed clock oscillates, the CPU stops operation until oscillation of the low-speed clock starts.
XTL
oscillation waveform
), see Appendix C, “Electrical Characteristics”.
Power supply V
Low-speed clock
Low-speed clock
XTL
RESET_VRX
) and oscillation stabilization period (8192 counts) after powered on.
Operation of Low-Speed Clock Generation Circuit
RESET
LSCLK
DD
Figure 6-3 Operation of Low-Speed Clock Generation Circuit
XTL
) and low-speed clock (LSCLK) oscillation stabilization period. For STOP mode, see
T
XTL
: Oscillation start time
Low-speed oscillation
Count: 8192
Low-speed oscillation
Count: 4096
Low-speed clock oscillation waveform
Start of LSCLK
supply
6 – 7
LSCLK waveform
STOP
external interrupt
mode
Occurrence of
ML610Q428/ML610Q429 User’s Manual
T
XTL
Chapter 6 Clock Generation Circuit
: Oscillation start time
Low-speed oscillation
Count: 8192
Low-speed oscillation
Count: 4096
Low-speed clock oscillation waveform
Start of LSCLK
supply
LSCLK waveform
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