ML610Q429-NNNTBZ03A7 Rohm Semiconductor, ML610Q429-NNNTBZ03A7 Datasheet - Page 135
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ML610Q429-NNNTBZ03A7
Manufacturer Part Number
ML610Q429-NNNTBZ03A7
Description
MCU 8BIT 48K FLASH 128-TQFP
Manufacturer
Rohm Semiconductor
Datasheets
1.ML610Q482P-NNNTB03A7.pdf
(20 pages)
2.ML610Q428-NNNTBZ03A7.pdf
(32 pages)
3.ML610Q428-NNNTBZ03A7.pdf
(434 pages)
Specifications of ML610Q429-NNNTBZ03A7
Core Processor
nX-U8/100
Core Size
8-Bit
Speed
4.2MHz
Connectivity
I²C, SSP, UART/USART
Peripherals
LCD, Melody Driver, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 2x12b, 2x24b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ML610Q429-NNNTBZ03A7
Manufacturer:
Rohm
Quantity:
900
Company:
Part Number:
ML610Q429-NNNTBZ03A7
Manufacturer:
Rohm Semiconductor
Quantity:
10 000
- ML610Q482P-NNNTB03A7 PDF datasheet
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P02/EXI2/RXD0/PWM2
P44/T02P0CK/PWM0
P45/T13P1CK/PWM1
10.
10.1 Overview
10.1.1
• The PWMn signals with the periods of approximately 488 ns (HTBCLK=4.096MHz) to 2s (@LSCLK=32.768kHz)
• The output logic of the PWMn signal can be switched to the positive or negative logic.
• At the coincidence of PWMn signal period, duties, and period & duty, a PWM interrupt (PWnINT) occurs.
• For the PWMn clock, a low-speed clock (LSCLK), a high-speed time base clock (HTBCLK), and an external clock
10.1.2
This LSI includes 3 channels of 16-bit PWM (Pulse Width Modulation).
The PWMn(n=0 to 2) output function is assigned to P43(Port 4) and P34(Port 3) as the tertiary function. For the
functions of port0, port 4 and port3, see Chapter 16, “Port0”, Chapter 20, “Port 4” and Chapter 19, “Port 3”.
Figure 10 - 1 shows the configuration of the PWMn circuit.
can be generated and output outside of the LSI.
are available.
External clock
PWM
Features
Configuration
PWnPL:
PWnPH:
PWnPBUF:
PWnDL:
PWnDH:
PWnDBUF:
PWnCL:
PWnCH:
PWnCON0:
PWnCON1:
Write PWnCH
HTBCLK
Read PWnCL
Write PWnCL
LSCLK
Data bus
PWMn period register L
PWMn period register H
PWMn period buffer
PWMn duty register L
PWMn duty register H
PWMn duty buffer
PWMn counter register L
PWMn counter register H
PWMn control register 0
PWMn control register 1
Figure 10-1 Configuration of PWMn Circuit
PWnCON0
PWnCON1
PnCK
PnFLG
PWnCH
R
latch
10 – 1
PWnCH/L
8
16
8
PnNEG
ML610Q428/ML610Q429 User’s Manual
Comparator
PWnPBUF
PWnPH/L
Output control
8
Period
match
circuit
16
8
Comparator
PWnDBUF
PWnDH/L
Duty
match
8
Chapter 10 PWM
PWnINT
16
8
n = 0 to 2
P43/PWM0
P34/PWM0
P47/PWM1
P35/PWM1
P30/PWM2
P20/PWM2
or
or
or
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