ML610Q429-NNNTBZ03A7 Rohm Semiconductor, ML610Q429-NNNTBZ03A7 Datasheet - Page 205
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ML610Q429-NNNTBZ03A7
Manufacturer Part Number
ML610Q429-NNNTBZ03A7
Description
MCU 8BIT 48K FLASH 128-TQFP
Manufacturer
Rohm Semiconductor
Datasheets
1.ML610Q482P-NNNTB03A7.pdf
(20 pages)
2.ML610Q428-NNNTBZ03A7.pdf
(32 pages)
3.ML610Q428-NNNTBZ03A7.pdf
(434 pages)
Specifications of ML610Q429-NNNTBZ03A7
Core Processor
nX-U8/100
Core Size
8-Bit
Speed
4.2MHz
Connectivity
I²C, SSP, UART/USART
Peripherals
LCD, Melody Driver, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 2x12b, 2x24b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ML610Q429-NNNTBZ03A7
Manufacturer:
Rohm
Quantity:
900
Company:
Part Number:
ML610Q429-NNNTBZ03A7
Manufacturer:
Rohm Semiconductor
Quantity:
10 000
- ML610Q482P-NNNTB03A7 PDF datasheet
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- ML610Q428-NNNTBZ03A7 PDF datasheet #3
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- Download datasheet (3Mb)
14.
14.1 Overview
14.1.1
• Master function
• Communication speeds supported include standard mode (100 kbps@1MHz HSCLK, 50kbps@500kHz HSCLK) and
• Allows support for arbitration function (multi-master) and clock synchronization (handshake).
• 7-bit address format (10-bit address can be supported)
14.1.2
14.1.3
This LSI includes 1 channel of I
The secondary functions of Port 4 are assigned to the I
clock input/output pin. For Port4, see Chapter 20, “Port 4”.
Figure 14-1 shows the configuration of the I
fast mode (400kbps@4MHz HSCLK).
I
2
Features
Configuration
List of Pins
C Bus Interface
Data bus
I2C0RD
I2C0SA
I2C0TD
I2C0CON
I2C0MOD
I2C0STAT
HSCLK
Pin name
P40/SDA
P41/SCL
: I
: I
: I
: I
: I
: I
2
2
2
2
2
2
C bus 0 receive register
C bus 0 slave address register
C bus 0 transmit data register
C bus 0 control register
C bus 0 mode register
C bus 0 status register
Generator
I2C0MOD
Figure 14-1 Configuration of I
2
Clock
C bus interface (master).
I/O
I/O
I/O
I
Used for the secondary function of the P40 pin.
I
Used for the secondary function of the P41 pin.
2
2
C bus interface data input/output pin.
C bus interface clock input/output pin.
2
C bus interface.
I2C0RD, I2C0STAT
I2C0SA
Shift Register
14 – 1
2
C bus interface data input/output pin and the I
I2C0TD
2
C Bus Interface
ML610Q428/ML610Q429 User’s Manual
Description
Controller
Controller
I2C0CON
SDA
SCL
I2C
Chapter 14 I
P41/SCL
P40/SDA
I2C0INT
2
C Bus Interface
2
C bus interface
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