ML610Q429-NNNTBZ03A7 Rohm Semiconductor, ML610Q429-NNNTBZ03A7 Datasheet - Page 87

• Manufacturer Part Number: ML610Q429-NNNTBZ03A7
• Description: MCU 8BIT 48K FLASH 128-TQFP
• Manufacturer: Rohm Semiconductor

Specifications of ML610Q429-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 4.2MHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.
6.1
6.1.1
• Low-speed clock: 32.768 kHz crystal oscillation mode
• High-speed clock: Software selection
6.1.2
The clock generation circuit generates and provides a low-speed clock (LSCLK), 2× low-speed clock (LSCLK2), a
high-speed clock (HSCLK), a system clock (SYSCLK), and a high-speed output clock (OUTCLK).
LSCLK×2, and HSCLK are time base clocks for the peripheral circuits, SYSCLK is a basic operation clock of CPU,
and OUTCLK is a clock that is output from a port.
For the OUTCLK output port, see Chapter 18, “Port 2”.
Additionally, for the STOP mode described in this chapter, see Chapter 4, “MCU Control Function”, and for BLD, see
Chapter 25, “Battery Level Detection Circuit”.
Figure 6-1 shows the configuration of the clock generation circuit.
Note:
This LSI starts operation with a clock generated by dividing the 500 kHz RC oscillation frequency by 8 after power-on
or a system reset. At initialization by software, set the FCON0 or FCON1 register to switch the clock to a required
one. Operation of this LSI is not guaranteed under a condition where a low-speed clock is not supplied.
− Capable of generating LSCLK × 2 (64 kHz) to be used for some peripherals.
− 500 kHz RC oscillation mode
− Crytal/ceramic oscillation mode
− Built-in PLL oscillation mode
− External clock input mode
− 2 MHz RC oscillation mode
FCON0
FCON1
Clock Generation Circuit
Overview
P10/OSC0
P11/OSC1
Features
Configuration
XT0
XT1
: Frequency control register 0
: Frequency control register 1
clock generation
clock generation
High-speed
Low-speed
circuit
circuit
Figure 6-1 Configuration of Clock Generation Circuit
OSCLK
FCON0, FCON1
1/1, 1/2, 1/4, 1/8
1/1, 1/2, 1/4, 1/8
Divide ratio
Divide ratio
selection
selection
6 – 1
ML610Q428/ML610Q429 User’s Manual
Chapter 6 Clock Generation Circuit
System clock
(SYSCLK)
2
(LSCLK
Low-speed clock
(LSCLK)
High-speed clock
(HSCLK)
High-speed output clock
(OUTCLK)
Data bus
×
low-speed clock
×
2)
LSCLK,