ADXL180WCPZ-RL Analog Devices Inc, ADXL180WCPZ-RL Datasheet - Page 47

• Manufacturer Part Number: ADXL180WCPZ-RL
• Description: IC ACCELEROMETER CONFIG 16-LFCSP
• Manufacturer: Analog Devices Inc
• Series: iMEMS®r

Specifications of ADXL180WCPZ-RL

• Axis: X or Y
• Acceleration Range: ±50g, 100g, 150g, 200g, 250g, 350g, 500g
• Voltage - Supply: 5 V ~ 14.5 V
• Output Type: Analog
• Bandwidth: 100Hz ~ 800Hz Selectable
• Mounting Type: Surface Mount
• Package / Case: 16-LFQFN, CSP Exposed Pad
• Package Type: LFCSP EP
• Operating Supply Voltage (min): 5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 125C
• Operating Temperature Classification: Automotive
• Product Depth (mm): 5mm
• Product Height (mm): 1.43mm
• Product Length (mm): 5mm
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Sensitivity: -
• Interface: -
• Lead Free Status / Rohs Status: Compliant
• Other names: ADXL180WCPZ-RLCT

CONFIGURATION MODE TRANSMIT
COMMUNICATIONS PROTOCOL
In configuration mode, the ADXL180 transmits the configura-
tion mode register data through the current mode Manchester
encoded serial port. The configuration mode protocol is fixed
regardless of the actual settings of the configuration registers
(RAM or OTP). The transmit communication protocol used by
the ADXL180 in configuration mode is
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Manchester-1 data encoding
Two start bits (10b)
4-bit configuration mode register address field
8-bit configuration mode register data field
3-bit state vector field (101b)
One parity bit (even)
Synchronization pulse disabled
Auto-zero disabled
Data is transmitted LSB first
TRANSMITTED
FIRST
START
1
BITS
0
Figure 38. Configuration Mode Transmit Data Frame
0
VECTOR
STATE
1
2
Rev. A | Page 47 of 60
0
1
DATA FRAME (18 BITS)
2
3
DATA
This is an 18-bit protocol (including the two start bits). Although
similar to the ADIFX protocol, it is different in that parity, and
not CRC, is used as the error checking code. This distinguishes
configuration mode messages from normal operation messages.
Figure 38 shows the configuration mode data frame format.
Table 42 shows the configuration mode transmit data bit mapping.
Excluding the two start bits, the word is 16 bits long. Data Bit
DB15 (transmitted last) is the parity bit. The configuration
mode transmit parity is even. The parity bit is set to either 1 or
0 to make the total number of 1s in the 16-bit word an even
number. Data Bits[DB14:DB11] are the four configuration
mode register address bits. The following eight data bits, DB10
through DB3, are the eight configuration mode register data
bits. The next three bits, DB2 through DB0, are the state vector
bits. In the configuration mode, the state vector is 101b. This
data frame format is different from the ADIFX format.
4
5
6
7
0
ADDRESS
1
2
3
P
0
ADXL180